diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-14 18:42:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-17 15:02:28 +0000 |
| commit | 2878c0b6dcc4d0dd9e0823cb63e9258f8b3655dc (patch) | |
| tree | b41f8b064bb40d107f32486a2cb13a7b49eee45a /src/northbridge | |
| parent | b572c9d5e553c0cefc9d2f43c924430324a6eaaf (diff) | |
nb/intel/nehalem: use pmclib to detect S3 resume
During the raminit the CPU gets reset, so reprogram those bits in
PM1_CNT such that the CPU remains aware that this is a S3 resume path
after the reset.
Change-Id: I8f5cafa235c8ab0d0a59fbeeee3465ebca4cc5d0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/nehalem/raminit.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/romstage.c | 21 |
2 files changed, 11 insertions, 16 deletions
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 46189117a7..c887de1d98 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -36,6 +36,7 @@ #include <cpu/intel/turbo.h> #include <mrc_cache.h> #include <southbridge/intel/ibexpeak/me.h> +#include <southbridge/intel/common/pmbase.h> #include <delay.h> #include <types.h> @@ -4246,6 +4247,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap) MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"? /* This issues a CPU reset without resetting the platform */ printk(BIOS_DEBUG, "Issuing a CPU reset\n"); + /* Write back the S3 state to PM1_CNT to let the reset CPU + know it also needs to take the s3 path. */ + if (s3resume) + write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) + | (SLP_TYP_S3 << 10)); MCHBAR32_OR(0x1af0, 0x10); halt(); } diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c index 8188303877..69383e6520 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/nehalem/romstage.c @@ -28,6 +28,7 @@ #include <device/device.h> #include <northbridge/intel/nehalem/chip.h> #include <northbridge/intel/nehalem/raminit.h> +#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/me.h> @@ -47,24 +48,12 @@ void mainboard_romstage_entry(void) early_pch_init(); - /* Read PM1_CNT, DON'T CLEAR IT or raminit will fail! */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - printk(BIOS_DEBUG, "a2: %02x\n", reg8); + s3resume = southbridge_detect_s3_resume(); + if (s3resume) { + u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + s3resume = 0; printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } } } |