diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-05-25 16:00:08 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-05-25 16:00:08 +0000 |
| commit | 2b01a8a5cd84af76e0b4ad7cc0ffc22e1e2f5146 (patch) | |
| tree | 992c192a2339c57e195e55130e7a32fe0946e636 /src/northbridge/intel | |
| parent | ba818172cb33cdd72a2cafd32056d7e41dceca92 (diff) | |
cosmetics.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/i440bx/raminit.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 9a8be8520b..d05f6fd8c9 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -22,9 +22,9 @@ #define RAMINIT_H /* The 440BX supports up to four (single- or double-sided) DIMMs. */ -#define DIMM_SOCKETS 4 +#define DIMM_SOCKETS 4 /* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */ -#define DIMM_SPD_BASE 0x50 +#define DIMM_SPD_BASE 0x50 #endif /* RAMINIT_H */ |