diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-04 13:59:29 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-11 12:21:25 +0000 |
| commit | 2437fe9dfab8e4056b633a39d51d07aa81ab3c9d (patch) | |
| tree | 1dd071659a48c99c1e71ddf03b8cdf416da324c2 /src/northbridge/intel | |
| parent | cbe5357de02fa9f25ab9c0ca557e3057c701b059 (diff) | |
sb/intel/i82801gx: Move CIR init to a common place
Some boards with the G41 chipset lacked programming CIR, so this
change add that to those boards too.
Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/pineview/early_init.c | 22 |
1 files changed, 2 insertions, 20 deletions
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index be6a5e27d6..1638f0e15a 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -135,26 +135,8 @@ static void early_misc_setup(void) pci_write_config8(LPC, 0x8, 0x1d); pci_write_config8(LPC, 0x8, 0x0); RCBA32(0x3410) = 0x00020465; - RCBA32(0x88) = 0x0011d000; - RCBA32(0x1fc) = 0x60f; - RCBA32(0x1f4) = 0x86000040; - RCBA32(0x214) = 0x10030509; - RCBA32(0x218) = 0x00020504; - RCBA32(0x220) = 0xc5; - RCBA32(0x3430) = 0x1; - RCBA32(0x2027) = 0x38f6a70d; - RCBA16(0x3e08) = 0x0080; - RCBA16(0x3e48) = 0x0080; - RCBA32(0x3e0e) = 0x00000080; - RCBA32(0x3e4e) = 0x00000080; - RCBA32(0x2034) = 0xb24577cc; - RCBA32(0x1c) = 0x03128010; - RCBA32(0x2010) = 0x400; - RCBA32(0x3400) = 0x4; - RCBA32(0x2080) = 0x18006007; - RCBA32(0x20a0) = 0x18006007; - RCBA32(0x20c0) = 0x18006007; - RCBA32(0x20e0) = 0x18006007; + + ich7_setup_cir(); pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1); pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1); |