diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-14 10:05:06 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-17 07:46:58 +0000 |
| commit | 8e679f72e9e496dc84f463d56577f8edc6ab744e (patch) | |
| tree | 1d7e2697bdba8b5e0b4550f5dbfc867b6e8ef175 /src/northbridge/intel | |
| parent | 806b2cd42b94b548a5bfa69a7e9c0cf2fda20f7f (diff) | |
sb/intel/i82801dx: Improve LPC device early init
Make the implementation more similar to i82801gx, enabling
ACPI PM and GPIO register spaces already in bootblock.
Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/e7505/romstage.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/northbridge/intel/e7505/romstage.c b/src/northbridge/intel/e7505/romstage.c index df10f9dbcf..d997ee19a8 100644 --- a/src/northbridge/intel/e7505/romstage.c +++ b/src/northbridge/intel/e7505/romstage.c @@ -8,10 +8,9 @@ void mainboard_romstage_entry(void) { - /* Perform some early chipset initialization required - * before RAM initialization can work - */ + /* FIXME: Keep until flashed bootblock has these. */ i82801dx_early_init(); + i82801dx_lpc_setup(); sdram_initialize(); |