diff options
| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2010-08-22 19:54:26 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-08-22 19:54:26 +0000 |
| commit | 4793ef1f824a2143443c5e2fe63b44deaae7dba7 (patch) | |
| tree | 24b84ede5519acf3cec3a63c52d94b9a90001409 /src/northbridge/intel | |
| parent | 213ab94ea4bd23f4b5f2b00a09a535925fe2c6a6 (diff) | |
documented workaround erratum 414, see
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
with patch.erratum414 it stops here (next patches don't make it get further,
but they're needed according to documentation, don't break anything for me and
I still don't have a solution for booting, so I'm keeping them there in case
they fix something.
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Loading stage image.
Check CBFS header at fffffd2e
magic is 4f524243
Found CBFS header at fffffd2e
Check fallback/romstage
CBFS: follow chain: fff00000 + 38 + 15b41 + align -> fff15b80
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x200000 (1114112 bytes), entry @
0x20000
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel')
0 files changed, 0 insertions, 0 deletions