diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-12-17 11:22:57 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-14 18:24:20 +0100 |
| commit | df7be71374a8b80708c58fd13e26b9e3fc6ed54c (patch) | |
| tree | 7d106d7fe952c9164fe818331a4823b74d2e2b89 /src/northbridge/intel | |
| parent | fb9928f2ec240babb5d3138136c03a7a78c53cc4 (diff) | |
haswell: Add ULT device IDs
Device IDs for northbridge and GPU.
Also mask off the lock bit in the memory map registers.
Change-Id: I9a4955d4541b938285712e82dd0b1696fa272b63
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2646
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 18 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 12 |
2 files changed, 24 insertions, 6 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 55c0d755cb..31f4dcc3af 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -223,9 +223,21 @@ static struct device_operations gma_func0_ops = { .ops_pci = &gma_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112, - 0x0116, 0x0122, 0x0126, 0x0166, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x0402, /* Desktop GT1 */ + 0x0412, /* Desktop GT2 */ + 0x0422, /* Desktop GT3 */ + 0x0406, /* Mobile GT1 */ + 0x0416, /* Mobile GT2 */ + 0x0426, /* Mobile GT3 */ + 0x0d16, /* Mobile 4+3 GT1 */ + 0x0d26, /* Mobile 4+3 GT2 */ + 0x0d36, /* Mobile 4+3 GT3 */ + 0x0a06, /* ULT GT1 */ + 0x0a16, /* ULT GT2 */ + 0x0a26, /* ULT GT3 */ + 0, +}; static const struct pci_driver pch_lpc __pci_driver = { .ops = &gma_func0_ops, diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 52b24bae04..5731077999 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -175,15 +175,15 @@ static void pci_domain_set_resources(device_t dev) /* Top of Upper Usable DRAM, including remap */ touud = pci_read_config32(dev, TOUUD+4); touud <<= 32; - touud |= pci_read_config32(dev, TOUUD); + touud |= pci_read_config32(dev, TOUUD) & ~1; /* Top of Lower Usable DRAM */ - tolud = pci_read_config32(dev, TOLUD); + tolud = pci_read_config32(dev, TOLUD) & ~1; /* Top of Memory - does not account for any UMA */ tom = pci_read_config32(dev, 0xa4); tom <<= 32; - tom |= pci_read_config32(dev, 0xa0); + tom |= pci_read_config32(dev, 0xa0) & ~1; printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", touud, tolud, tom); @@ -467,6 +467,12 @@ static const struct pci_driver mc_driver_hsw_mobile __pci_driver = { .device = 0x0c04, /* Mobile Haswell */ }; +static const struct pci_driver mc_driver_hsw_ult __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0a04, /* ULT Haswell */ +}; + static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); |