intel/e7505,i82801dx: Refactor raminit

Avoid direct enable_smbus() call from northbridge code.

Change-Id: I077e455242db9fc0f86432bd1afab75cb6fb6f4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

3 files changed, 34 insertions, 43 deletions

diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 972a2f37ee..7953aca3b1 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -1740,28 +1740,38 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 		d060_control(D060_CMD_1);
 }
 
-/**
- *
- *
- */
-void e7505_mch_init(const struct mem_controller *memctrl)
+static int e7505_mch_is_ready(void)
 {
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	sdram_set_registers(memctrl);
-	sdram_set_spd_registers(memctrl);
-	sdram_enable(memctrl);
+	uint32_t dword = pci_read_config32(MCHDEV, DRC);
+	return !!(dword & DRC_DONE);
 }
 
-void e7505_mch_done(const struct mem_controller *memctrl)
+void sdram_initialize(void)
 {
-	sdram_post_ecc(memctrl);
+	static const struct mem_controller memctrl[] = {
+		{
+			.d0 = PCI_DEV(0, 0, 0),
+			.d0f1 = PCI_DEV(0, 0, 1),
+			.channel0 = { 0x50, 0x52, 0, 0 },
+			.channel1 = { 0x51, 0x53, 0, 0 },
+		},
+	};
 
-	timestamp_add_now(TS_AFTER_INITRAM);
-}
+	/* If this is a warm boot, some initialisation can be skipped */
+	if (!e7505_mch_is_ready()) {
 
-int e7505_mch_is_ready(void)
-{
-	uint32_t dword = pci_read_config32(MCHDEV, DRC);
-	return !!(dword & DRC_DONE);
+		/* The real MCH initialisation. */
+		timestamp_add_now(TS_BEFORE_INITRAM);
+
+		sdram_set_registers(memctrl);
+		sdram_set_spd_registers(memctrl);
+		sdram_enable(memctrl);
+
+		/* Hook for post ECC scrub settings and debug. */
+		sdram_post_ecc(memctrl);
+
+		timestamp_add_now(TS_AFTER_INITRAM);
+	}
+
+	printk(BIOS_DEBUG, "SDRAM is up.\n");
 }
diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h
index c65675f820..9aa6eb4b8e 100644
--- a/src/northbridge/intel/e7505/raminit.h
+++ b/src/northbridge/intel/e7505/raminit.h
@@ -30,8 +30,6 @@ struct mem_controller {
 	uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL];
 };
 
-void e7505_mch_init(const struct mem_controller *memctrl);
-void e7505_mch_done(const struct mem_controller *memctrl);
-int e7505_mch_is_ready(void);
+void sdram_initialize(void);
 
 #endif /* RAMINIT_H */
diff --git a/src/northbridge/intel/e7505/romstage.c b/src/northbridge/intel/e7505/romstage.c
index 6c74c1febf..f506bf4894 100644
--- a/src/northbridge/intel/e7505/romstage.c
+++ b/src/northbridge/intel/e7505/romstage.c
@@ -13,9 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <stdint.h>
 #include <cbmem.h>
-#include <console/console.h>
 #include <arch/romstage.h>
 
 #include <southbridge/intel/i82801dx/i82801dx.h>
@@ -23,27 +21,12 @@
 
 void mainboard_romstage_entry(void)
 {
-	static const struct mem_controller memctrl[] = {
-		{
-			.d0 = PCI_DEV(0, 0, 0),
-			.d0f1 = PCI_DEV(0, 0, 1),
-			.channel0 = { 0x50, 0x52, 0, 0 },
-			.channel1 = { 0x51, 0x53, 0, 0 },
-		},
-	};
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	i82801dx_early_init();
 
-	/* If this is a warm boot, some initialization can be skipped */
-	if (!e7505_mch_is_ready()) {
-		enable_smbus();
-
-		/* The real MCH initialisation. */
-		e7505_mch_init(memctrl);
-
-		/* Hook for post ECC scrub settings and debug. */
-		e7505_mch_done(memctrl);
-	}
-
-	printk(BIOS_DEBUG, "SDRAM is up.\n");
+	sdram_initialize();
 
 	cbmem_recovery(0);
 }