diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2021-01-05 14:38:57 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2021-01-21 09:08:14 +0000 |
| commit | 985821c4f2feda41ed2d1ab83f6ae7b8f15197bd (patch) | |
| tree | 53af8c6c11a980690639e87e60cf5dc139a2baa0 /src/northbridge/intel/x4x | |
| parent | 083702c32ed2e70fd49ec7b02a79731173970a6d (diff) | |
cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE
Increase DCACHE_RAM_SIZE to 32kB and remove "NO_CBFS_MCACHE".
It’s quite safe to increase DCACHE_RAM_SIZE. All LGA775 targets
should have at least 256K L2 cache. That is plenty for XIP RO cache of
bootblock + romstage and a 32K CAR.
Change-Id: I393b2727bd90a990c3108a4dbead62b17d7fc531
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 8226fe90ee..00e9a3ad21 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -13,7 +13,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select CACHE_MRC_SETTINGS select PARALLEL_MP select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES - select NO_CBFS_MCACHE config CBFS_SIZE hex |