nb/intel/x4x: Put stage cache in TSEG

TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.

Tested on Intel DG41WV, the stage cache gets properly created and used
on S3 resume.

Change-Id: Ie46c1416f8042d5571339b36e1253c0cae0684b8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25606
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 32 insertions, 0 deletions

diff --git a/src/northbridge/intel/x4x/stage_cache.c b/src/northbridge/intel/x4x/stage_cache.c
new file mode 100644
index 0000000000..ff752e5d11
--- /dev/null
+++ b/src/northbridge/intel/x4x/stage_cache.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <device/pci.h>
+#include <stage_cache.h>
+#include <cpu/intel/smm/gen1/smi.h>
+#include "x4x.h"
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+	/*
+	 * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+	 * The top of RAM is defined to be the TSEG base address.
+	 */
+	*size = CONFIG_SMM_RESERVED_SIZE;
+	*base = (void *)(northbridge_get_tseg_base()
+			 + CONFIG_SMM_RESERVED_SIZE);
+}