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authorJakub Czapiga <jacz@semihalf.com>2022-02-15 11:50:31 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-03-08 16:06:33 +0000
commitad6157ebdfddc39b95e388487e00cadd2bbf368b (patch)
treebbb85c9b13faf74515387ee8978eefd6d79e6b06 /src/northbridge/intel/x4x/raminit.c
parente96ade6981c60af4d6f24471d7f6a440ab7bfd4e (diff)
timestamps: Rename timestamps to make names more consistent
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/northbridge/intel/x4x/raminit.c')
-rw-r--r--src/northbridge/intel/x4x/raminit.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 460916b421..2f844a5b36 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -566,7 +566,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
int fast_boot, cbmem_was_inited;
size_t mrc_size;
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
printk(BIOS_DEBUG, "Setting up RAM controller.\n");
pci_write_config8(HOST_BRIDGE, 0xdf, 0xff);
@@ -638,7 +638,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
pci_or_config8(HOST_BRIDGE, 0xf4, 1);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
printk(BIOS_DEBUG, "RAM initialization finished.\n");