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| author | Patrick Georgi <patrick@georgi-clan.de> | 2012-02-16 18:54:37 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-12 00:06:11 +0200 |
| commit | 2c2e78d845cd28eb3b11c87fa3feafaf836cda7a (patch) | |
| tree | 8eac7f9467d2c13860ae1d23152c9443367b4b85 /src/northbridge/intel/sch | |
| parent | 5c1ff9284a7ac382a9ec702fa52f3a173279d566 (diff) | |
Unify IO APIC address specification
Some places still hardcoded the address instead of using IO_APIC_ADDR.
Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sch')
| -rw-r--r-- | src/northbridge/intel/sch/acpi/hostbridge.asl | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/intel/sch/acpi/hostbridge.asl b/src/northbridge/intel/sch/acpi/hostbridge.asl index 7e92a0e671..44a8be04d5 100644 --- a/src/northbridge/intel/sch/acpi/hostbridge.asl +++ b/src/northbridge/intel/sch/acpi/hostbridge.asl @@ -19,6 +19,7 @@ * MA 02110-1301 USA */ +#include <arch/ioapic.h> Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI @@ -211,7 +212,7 @@ Method (_CRS, 0, Serialized) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0xfec00000,,, PM01) + IO_APIC_ADDR,,, PM01) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |