diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-25 17:05:20 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-16 20:22:54 +0000 |
| commit | bf7435087eee94a6cbd5f50d816fea9168395090 (patch) | |
| tree | 8cf2ca40d7f0c9474f96bd6b671aa8a07bf46129 /src/northbridge/intel/sandybridge | |
| parent | 25b35d317eef9ef5d73bbecc502fdac13a478bf6 (diff) | |
sb/intel/sandybridge/early_pch: Make DMI init more readable
Add a few comments and use known register values.
Based on the "2nd Generation Intel® Core™ Processor Family Mobile"
datasheet and the existing serialice trace.
Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to GNU/Linux.
Change-Id: I404515b77a22324f55581f117d79630be4ba64dd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32071
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 92cb888a41..77f2ead74e 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -175,12 +175,23 @@ enum platform_type { #define DMIPVCCCTL 0x00c /* 16bit */ #define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL0 0x014 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ #define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP 0x2 #define DMIVC1RCAP 0x01c /* 32bit */ #define DMIVC1RCTL 0x020 /* 32bit */ #define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP 0x2 + +#define DMIVCPRCTL 0x02c /* 32bit */ + +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP 0x2 + +#define DMIVCMRCTL 0x0038 /* 32 bit */ +#define DMIVCMRSTS 0x003e /* 16 bit */ +#define VCMNP 0x2 #define DMILE1D 0x050 /* 32bit */ #define DMILE1A 0x058 /* 64bit */ @@ -190,7 +201,7 @@ enum platform_type { #define DMILCAP 0x084 /* 32bit */ #define DMILCTL 0x088 /* 16bit */ #define DMILSTS 0x08a /* 16bit */ - +#define TXTRN (1 << 11) #define DMICTL1 0x0f0 /* 32bit */ #define DMICTL2 0x0fc /* 32bit */ |