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authorStefan Reinauer <stefan.reinauer@coreboot.org>2013-02-27 23:45:20 +0100
committerRonald G. Minnich <rminnich@gmail.com>2013-02-28 00:00:30 +0100
commitfd611f9c2c8c751069c6cd1634a3e3e523ff098b (patch)
tree3e1d3d844987a6f02d406e13f68aa37e3f55ec7e /src/northbridge/intel/i945
parent9c29cfae8cc6214478a0a555e6901779eb19ef54 (diff)
Drop CONFIG_WRITE_HIGH_TABLES
It's been on for all boards per default since several years now and the old code path probably doesn't even work anymore. Let's just have one consistent way of doing things. Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2547 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/i945')
-rw-r--r--src/northbridge/intel/i945/northbridge.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 63a03adc5d..bf3bbcb1c6 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -26,6 +26,7 @@
#include <device/hypertransport.h>
#include <stdlib.h>
#include <string.h>
+#include <cbmem.h>
#include <cpu/cpu.h>
#include <arch/acpi.h>
#include "i945.h"
@@ -80,10 +81,6 @@ static void add_fixed_resources(struct device *dev, int index)
}
}
-#if CONFIG_WRITE_HIGH_TABLES
-#include <cbmem.h>
-#endif
-
static void pci_domain_set_resources(device_t dev)
{
uint32_t pci_tolm;
@@ -173,11 +170,9 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
-#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
-#endif
}
/* TODO We could determine how many PCIe busses we need in