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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-17 20:51:08 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-26 21:08:41 +0000 |
| commit | cd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf (patch) | |
| tree | b0438431df0943ab5f0fa9d80a99fc265130ac23 /src/northbridge/intel/haswell | |
| parent | 16248e89ecf73a76e5d9e9e2de46146f7ffece88 (diff) | |
soc/intel: Use common romstage code
This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/memmap.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index b1d86db51a..5bc74f8703 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -18,10 +18,10 @@ #include <arch/romstage.h> #include <console/console.h> +#include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <device/pci_ops.h> #include <cbmem.h> -#include <cpu/intel/romstage.h> #include <stage_cache.h> #include "haswell.h" |