diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2022-01-31 16:47:54 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-04 20:10:51 +0000 |
| commit | 8b94d3e9d94b5c9a7add46e95e3e2fb9ebaa60e6 (patch) | |
| tree | fd6b3071ee33e6dbf56d492f4d08c78e74b36a97 /src/northbridge/intel/haswell | |
| parent | cd8771640feb4c5d05104bae26134b20f7e8c9f6 (diff) | |
nb/intel/haswell: Report SMBIOS memory speed in MT/s
The memory speed values in SMBIOS tables are expressed in MT/s, not MHz.
Adjust the reported frequency values accordingly.
Change-Id: If34827fee582ef10057e7540b9d23d8c74bd2a32
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61504
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/haswell_mrc/raminit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index e46eb57826..fedb6832e9 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -234,7 +234,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) memset(mem_info, 0, sizeof(struct memory_info)); - const u32 ddr_frequency = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; + const u32 ddr_freq_mhz = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; for (ch = 0; ch < NUM_CHANNELS; ch++) { const u32 ch_conf = mchbar_read32(MAD_DIMM(ch)); @@ -246,7 +246,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) dimm = &mem_info->dimm[dimm_cnt]; dimm->dimm_size = dimm_size; dimm->ddr_type = MEMORY_TYPE_DDR3; - dimm->ddr_frequency = ddr_frequency; + dimm->ddr_frequency = ddr_freq_mhz * 2; /* In MT/s */ dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + d_num)) & 1); dimm->channel_num = ch; dimm->dimm_num = d_num; |