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authorElyes HAOUAS <ehaouas@noos.fr>2021-02-12 08:17:35 +0100
committerAngel Pons <th3fanbus@gmail.com>2021-02-16 20:56:56 +0000
commit030d338bb23459dfd2f3f710e92a4031845c0e13 (patch)
treeeea1df3e126f2ad25827b064ff4cd12463d8ec19 /src/northbridge/intel/gm45
parent06c761ca948544861ef50cb494a1043839259b5f (diff)
nb/intel: Add missing <types.h>
Add needed but missing <types.h>. Change-Id: I801be1ca8da4b1641941d5571d2aa298470f407b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50578 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r--src/northbridge/intel/gm45/memmap.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 4fe3998bee..28edb381a1 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -3,7 +3,6 @@
// Use simple device model for this file even in ramstage
#define __SIMPLE_DEVICE__
-#include <stdint.h>
#include <arch/romstage.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
@@ -13,6 +12,8 @@
#include <cbmem.h>
#include <program_loading.h>
#include <cpu/intel/smm_reloc.h>
+#include <types.h>
+
#include "gm45.h"
/*