diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-08-07 22:12:09 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-06-06 08:57:09 +0000 |
| commit | 750d57ff5dd7f7412c4526c87191bd1378a49d4a (patch) | |
| tree | a533cd5759cf3d005300a6796aee95754f4b32ec /src/northbridge/amd | |
| parent | df3d97e821e838323b9a846f01057c656047c3b3 (diff) | |
drivers/amd/agesa: Don't save regular boot MTRR to flash
Save the regular boot MTRRs that are restored on the S3 path during
the CPU init in cbmem instead of storing them to the SPI flash.
This was probably done because historically this code run with late
cbmem init (in ramstage).
TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine.
Change-Id: Ia58e7cd1afb785ba0c379ba75ef6090b56cb9dc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44294
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/agesa/agesa_helper.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index 5f93d2ad17..183a33052b 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -38,7 +38,7 @@ void EmptyHeap(void); void fixup_cbmem_to_UC(int s3resume); void restore_mtrr(void); -void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size); +void backup_mtrr(void); const void *OemS3Saved_MTRR_Storage(void); #endif /* _AGESA_HELPER_H_ */ |