diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-10 00:35:05 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-11-11 20:49:56 +0100 |
| commit | 010d62311ec4be4a61dc9ee394da39d908f1f7a8 (patch) | |
| tree | 39f9eac590546fbf9f1efe16bb912f196e8962fe /src/northbridge/amd | |
| parent | 0dc117aa5d0375f0ef94824ceab399c8fe94b136 (diff) | |
northbridge/amd/amdfam10: Add ability to set maximum P-state limit
Under specific circumstances, for instance in low power or fanless
machines, it may be useful to cap the maximum P-state of the CPU.
Allow the maximum CPU P-state to be set via an NVRAM option.
Change-Id: Ifdbb1ad11a856f855c59702ae0ee99e95b08520e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11985
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdfam10/misc_control.c | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 24c422d67e..847b599b33 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -120,16 +120,32 @@ static void mcf3_set_resources(device_t dev) static void misc_control_init(struct device *dev) { - u32 cmd; + uint32_t dword; + uint8_t nvram; + uint8_t boost_limit; + uint8_t current_boost; printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); /* Disable Machine checks from Invalid Locations. * This is needed for PC backwards compatibility. */ - cmd = pci_read_config32(dev, 0x44); - cmd |= (1<<6) | (1<<25); - pci_write_config32(dev, 0x44, cmd ); + dword = pci_read_config32(dev, 0x44); + dword |= (1<<6) | (1<<25); + pci_write_config32(dev, 0x44, dword); + + boost_limit = 0xf; + if (get_option(&nvram, "maximum_p_state_limit") == CB_SUCCESS) + boost_limit = nvram & 0xf; + + /* Set P-state maximum value */ + dword = pci_read_config32(dev, 0xdc); + current_boost = (dword >> 8) & 0x7; + if (boost_limit > current_boost) + boost_limit = current_boost; + dword &= ~(0x7 << 8); + dword |= (boost_limit & 0x7) << 8; + pci_write_config32(dev, 0xdc, dword); printk(BIOS_DEBUG, "done.\n"); } |