diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-02 19:22:00 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-12 20:08:19 +0200 |
| commit | 6e8b3c11105682e58ccb0574148654adecc532f7 (patch) | |
| tree | bcd395a865e9d3f981e5ef9e99ff7b8bbfea3fe5 /src/northbridge/amd/amdmct/mct_ddr3 | |
| parent | 6b72787d270077969869e9b17b88a63539f172b4 (diff) | |
src/northbridge: Improve code formatting
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16414
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 0c37366845..08d8d43ff3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2398,10 +2398,10 @@ static void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanosec tsc_msr = rdmsr(0x00000010); start_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo; - do { + do { tsc_msr = rdmsr(0x00000010); current_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo; - } while ((current_timestamp - start_timestamp) < cycle_count); + } while ((current_timestamp - start_timestamp) < cycle_count); } static void precise_memclk_delay_fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t clocks) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 324e35e980..802417971f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -930,7 +930,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, */ for (lane = 0; lane < 8; lane++) { if (trained[lane]) { - pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; + pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; } else { printk(BIOS_WARNING, "TrainRcvrEn: WARNING: Lane %d of receiver %d on channel %d failed training!\n", lane, Receiver, Channel); |