diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-06-26 20:17:50 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-02 16:14:36 +0000 |
| commit | 63f98f23045e072b0d07ecdd4cd50d01ad844df7 (patch) | |
| tree | cd0cff2a76b8b44b9563de0cf63f2e8b831e9735 /src/northbridge/amd/amdmct/mct_ddr3 | |
| parent | 7803e487bdd64ec0f1a8a17a483a4298d38bb77a (diff) | |
src: Use CRx_TYPE type for CRx
Change-Id: If50d9218119d5446d0ce98b8a9297b23bae65c72
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33816
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 5 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 7 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 4 |
3 files changed, 9 insertions, 7 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 34b13ea306..6b31294586 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -16,6 +16,7 @@ #include <inttypes.h> #include <console/console.h> +#include <cpu/x86/cr.h> #include <string.h> #include <arch/cpu.h> #include <cpu/amd/msr.h> @@ -405,7 +406,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, u32 dev; u32 addr; u8 valid; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u32 index_reg; uint32_t TestAddr; @@ -1617,7 +1618,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, u8 _Wrap32Dis = 0, _SSE2 = 0; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; uint8_t dct; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index a6faf90e0c..032152c39d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -22,6 +22,7 @@ #include <arch/cpu.h> #include <inttypes.h> #include <console/console.h> +#include <cpu/x86/cr.h> #include <string.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> @@ -612,7 +613,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, u32 index_reg; u32 ch_start, ch_end, ch; msr_t msr; - u32 cr4; + CRx_TYPE cr4; uint32_t dword; uint8_t dimm; @@ -1186,7 +1187,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, u32 index_reg; u32 ch_start, ch_end, ch; u32 msr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; uint32_t dword; @@ -1583,7 +1584,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, u32 index_reg; u32 ch_start, ch_end; u32 msr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; uint32_t dword; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index e7b7883f13..ec9b8e4327 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -21,7 +21,7 @@ #include <inttypes.h> #include <console/console.h> #include <cpu/amd/msr.h> - +#include <cpu/x86/cr.h> #include "mct_d.h" #include "mct_d_gcc.h" @@ -119,7 +119,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, u32 PatternBuffer[60]; /* FIXME: why not 48 + 4 */ u32 Margin; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u8 valid; |