diff options
author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-08 15:46:37 +0000 |
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committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-08 15:46:37 +0000 |
commit | af97d33ec426b9414133fd82d958cf9ab52a390f (patch) | |
tree | d99f6480914df848dabb0ec197864e0c8f64d939 /src/northbridge/amd/amdfam10/sspr1.asl | |
parent | 0e92974904703272b55d66dc4959d95adba6f30c (diff) |
Clean up ACPI:
- unify all iasl related rules into the toplevel Makefile
- build a filesystem standard for ACPI files and use it
- pass ACPI sources through cpp, so constants can be shared
between C and ACPI more easily
- use cpp's #include instead of ACPI's Include() so cpp gets
the whole picture
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdfam10/sspr1.asl')
-rw-r--r-- | src/northbridge/amd/amdfam10/sspr1.asl | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdfam10/sspr1.asl b/src/northbridge/amd/amdfam10/sspr1.asl new file mode 100644 index 0000000000..1bfdde018a --- /dev/null +++ b/src/northbridge/amd/amdfam10/sspr1.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441) +{ + Scope (\_SB) + { + Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated + { + Name(_PCT, Package () + { + ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL + ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS + }) + + Name(_PSS, Package() + { + Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, + }) + } + + } +} |