AGESA f15: Remove f10 references

Vendorcode for f15 also has f10 support, so
AMD_AGESA_FAMILY_10 was never selected.

Change-Id: I9a026c36ace88f1110a52d7e24d3e6ab36508932
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

2 files changed, 0 insertions, 146 deletions

diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h
deleted file mode 100644
index 27f78a3331..0000000000
--- a/src/northbridge/amd/agesa/family10/amdfam10.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef AMDFAM10_H
-#define AMDFAM10_H
-
-#include <cpu/x86/msr.h>
-
-#define HWCR_MSR                        0xC0010015
-#define NB_CFG_MSR                      0xC001001f
-#define LS_CFG_MSR                      0xC0011020
-#define IC_CFG_MSR                      0xC0011021
-#define DC_CFG_MSR                      0xC0011022
-#define BU_CFG_MSR                      0xC0011023
-#define BU_CFG2_MSR                     0xC001102A
-
-#define CPU_ID_FEATURES_MSR		0xC0011004
-#define CPU_ID_EXT_FEATURES_MSR		0xC0011005
-
-/* Definitions of various FAM10 registers */
-/* Function 0 */
-#define HT_TRANSACTION_CONTROL 0x68
-#define  HTTC_DIS_RD_B_P		(1 << 0)
-#define  HTTC_DIS_RD_DW_P		(1 << 1)
-#define  HTTC_DIS_WR_B_P		(1 << 2)
-#define  HTTC_DIS_WR_DW_P		(1 << 3)
-#define  HTTC_DIS_MTS			(1 << 4)
-#define  HTTC_CPU1_EN			(1 << 5)
-#define  HTTC_CPU_REQ_PASS_PW		(1 << 6)
-#define  HTTC_CPU_RD_RSP_PASS_PW	(1 << 7)
-#define  HTTC_DIS_P_MEM_C		(1 << 8)
-#define  HTTC_DIS_RMT_MEM_C		(1 << 9)
-#define  HTTC_DIS_FILL_P		(1 << 10)
-#define  HTTC_RSP_PASS_PW		(1 << 11)
-#define  HTTC_BUF_REL_PRI_SHIFT	13
-#define  HTTC_BUF_REL_PRI_MASK		3
-#define   HTTC_BUF_REL_PRI_64		0
-#define   HTTC_BUF_REL_PRI_16		1
-#define   HTTC_BUF_REL_PRI_8		2
-#define   HTTC_BUF_REL_PRI_2		3
-#define  HTTC_LIMIT_CLDT_CFG		(1 << 15)
-#define  HTTC_LINT_EN			(1 << 16)
-#define  HTTC_APIC_EXT_BRD_CST		(1 << 17)
-#define  HTTC_APIC_EXT_ID		(1 << 18)
-#define  HTTC_APIC_EXT_SPUR		(1 << 19)
-#define  HTTC_SEQ_ID_SRC_NODE_EN	(1 << 20)
-#define  HTTC_DS_NP_REQ_LIMIT_SHIFT	21
-#define  HTTC_DS_NP_REQ_LIMIT_MASK	3
-#define   HTTC_DS_NP_REQ_LIMIT_NONE	0
-#define   HTTC_DS_NP_REQ_LIMIT_1	1
-#define   HTTC_DS_NP_REQ_LIMIT_4	2
-#define   HTTC_DS_NP_REQ_LIMIT_8	3
-
-/* Function 1 */
-
-/* Function 2 */
-
-/* Function 3 */
-
-
-/* Function 5 for FBDIMM */
-#define LinkConnected		(1 << 0)
-#define InitComplete		(1 << 1)
-#define NonCoherent		(1 << 2)
-#define ConnectionPending	(1 << 4)
-
-#if CONFIG_MAX_PHYSICAL_CPUS > 8
-	#if CONFIG_MAX_PHYSICAL_CPUS > 32
-		#define NODE_NUMS 64
-	#else
-		#define NODE_NUMS 32
-	#endif
-#else
-	#define NODE_NUMS 8
-#endif
-
-#ifdef __PRE_RAM__
-#if NODE_NUMS == 64
-	 #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
-#else
-	 #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
-#endif
-#endif
-
-#endif /* AMDFAM10_H */
diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h
deleted file mode 100644
index 61de4d9895..0000000000
--- a/src/northbridge/amd/agesa/family10/reset_test.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * copy from src/northbridge/amd/amdfam10/reset_test.c
- */
-
-#ifndef _RESET_TEST_H_
-#define _RESET_TEST_H_
-
-#include <arch/io.h>
-#include "amdfam10.h"	/* NODE_PCI */
-
-#define NODE_ID			0x60
-#define HT_INIT_CONTROL		0x6c
-#define HTIC_ColdR_Detect	(1 << 4)
-#define HTIC_BIOSR_Detect	(1 << 5)
-#define HTIC_INIT_Detect	(1 << 6)
-
-static inline u32 warm_reset_detect(u8 nodeid)
-{
-	u32 htic;
-	pci_devfn_t device;
-	device = NODE_PCI(nodeid, 0);
-	htic = pci_io_read_config32(device, HT_INIT_CONTROL);
-	return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
-}
-
-static inline void distinguish_cpu_resets(u8 nodeid)
-{
-	u32 htic;
-	pci_devfn_t device;
-	device = NODE_PCI(nodeid, 0);
-	htic = pci_io_read_config32(device, HT_INIT_CONTROL);
-	htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
-	pci_io_write_config32(device, HT_INIT_CONTROL, htic);
-}
-
-#endif