diff options
| author | Shawn Nematbakhsh <shawnn@google.com> | 2013-03-14 11:03:59 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-21 23:18:00 +0100 |
| commit | 7b8952c19d8d809b7aeec629b31e1c3d66f19884 (patch) | |
| tree | b7f1970e1b90c7b1c8097e606326b75b75858bd3 /src/mainboard | |
| parent | 2b7c88f99ed55682378bc0b1aae8004e6e27fe7b (diff) | |
Butterfly, Stout: Force SATA link speed to 3 Gbps
Force link speed on these platforms to 3 Gbps to defeat buggy SATA
drives.
Change-Id: Ia38a7c486fb1f4469cd67ca5244bbf61f877d556
Signed-off-by: Shawn Nematbakhsh <shawnn@google.com>
Reviewed-on: http://review.coreboot.org/2823
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/butterfly/devicetree.cb | 5 | ||||
| -rw-r--r-- | src/mainboard/google/stout/devicetree.cb | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index ca8118abab..e7a50c0c57 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -58,7 +58,10 @@ chip northbridge/intel/sandybridge register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" - register "sata_port_map" = "0x3" #enable SATA ports 0 & 1 + # Enable SATA ports 0 & 1 + register "sata_port_map" = "0x3" + # Set max SATA speed to 3.0 Gb/s + register "sata_interface_speed_support" = "0x2" # Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index c58a8d69e9..6e02020890 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -60,6 +60,8 @@ chip northbridge/intel/sandybridge register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" + # Set max SATA speed to 3.0 Gb/s + register "sata_interface_speed_support" = "0x2" # Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069" |