summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorTarun Tuli <taruntuli@google.com>2022-10-25 18:57:34 +0000
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2023-02-22 00:45:55 +0000
commit2e6fa8206e0a3bdd2e53542b6377fe2b37e3f26e (patch)
treee8e91e0ce811788a112df0234aad1f8fd9382205 /src/mainboard
parent4843ded47c3e72ee112a1ea79f03017f6999c1e1 (diff)
mb/google/poppy: Nami - invoke power cycle of FPMCU on startup
Add functionality such that the FPMCU is power cycled long enough on boot to ensure proper reset. This solution relies solely on coreboot to sequence the power and reset signals appropriately (150ms on boot). BUG=b:245954151 TEST=Confirmed FPMCU is still functional on Nami. Confirmed power is off for 150ms seconds on boot. Confirmed RCC_CSR of FPMCU indicates power cycle occurred. Confirmed reset is de-asserted approx 3ms after power application (target >2.5ms) Change-Id: I21eb85dc11e0ea0eb5de8a6092b01663d3c3df91 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68820 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/poppy/variants/nami/gpio.c44
-rw-r--r--src/mainboard/google/poppy/variants/nami/mainboard.c35
2 files changed, 75 insertions, 4 deletions
diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c
index 8df93f208e..4ee19b68ae 100644
--- a/src/mainboard/google/poppy/variants/nami/gpio.c
+++ b/src/mainboard/google/poppy/variants/nami/gpio.c
@@ -404,7 +404,7 @@ static const struct pad_config fpmcu_gpio_table[] = {
/* B1 : CORE_VID1 ==> FPMCU_INT_L */
PAD_CFG_GPI_SCI(GPP_B1, UP_20K, DEEP, EDGE_SINGLE, INVERT),
/* B11 : EXT_PWR_GATE# ==> PCH_FP_PWR_EN */
- PAD_CFG_GPO(GPP_B11, 1, DEEP),
+ PAD_CFG_GPO(GPP_B11, 0, DEEP),
/* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS# */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
/* B20 : GSPI1_CLK ==> PCH_SPI_FP_CLK */
@@ -416,13 +416,48 @@ static const struct pad_config fpmcu_gpio_table[] = {
/* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */
PAD_CFG_GPO(GPP_C3, 0, DEEP),
/* C9 : UART0_TXD ==> FP_RST_ODL */
- PAD_CFG_GPO(GPP_C9, 1, DEEP),
+ PAD_CFG_GPO(GPP_C9, 0, DEEP),
/* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */
PAD_CFG_GPO(GPP_D5, 0, DEEP),
/* D17 : DMIC_CLK1 ==> NC */
PAD_NC(GPP_D17, NONE),
};
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+ uint32_t sku_id = variant_board_sku();
+ const struct pad_config *board_gpio_tables;
+
+ switch (sku_id) {
+ case SKU_0_EKKO:
+ case SKU_1_EKKO:
+ case SKU_2_EKKO:
+ case SKU_3_EKKO:
+ case SKU_4_EKKO:
+ case SKU_5_EKKO:
+ case SKU_6_EKKO:
+ case SKU_7_EKKO:
+ case SKU_0_BARD:
+ case SKU_1_BARD:
+ case SKU_2_BARD:
+ case SKU_3_BARD:
+ case SKU_4_BARD:
+ case SKU_5_BARD:
+ case SKU_6_BARD:
+ case SKU_7_BARD:
+ *num = ARRAY_SIZE(fpmcu_gpio_table);
+ board_gpio_tables = fpmcu_gpio_table;
+ break;
+ default:
+ /* Initialized in variant_sku_gpio_table */
+ *num = 0;
+ board_gpio_tables = NULL;
+ break;
+ }
+ return board_gpio_tables;
+}
+
+
const struct pad_config *variant_sku_gpio_table(size_t *num)
{
uint32_t sku_id = variant_board_sku();
@@ -468,8 +503,9 @@ const struct pad_config *variant_sku_gpio_table(size_t *num)
case SKU_5_BARD:
case SKU_6_BARD:
case SKU_7_BARD:
- *num = ARRAY_SIZE(fpmcu_gpio_table);
- board_gpio_tables = fpmcu_gpio_table;
+ /* Initialized in variant_romstage_gpio_table */
+ *num = 0;
+ board_gpio_tables = NULL;
break;
default:
*num = ARRAY_SIZE(nami_default_sku_gpio_table);
diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c
index b703d40fc3..a4634fc6e5 100644
--- a/src/mainboard/google/poppy/variants/nami/mainboard.c
+++ b/src/mainboard/google/poppy/variants/nami/mainboard.c
@@ -15,6 +15,8 @@
#include <soc/ramstage.h>
#include <string.h>
#include <variant/sku.h>
+#include <gpio.h>
+#include <delay.h>
#define PL2_I7_SKU 44
#define PL2_DEFAULT 29
@@ -299,3 +301,36 @@ void variant_devtree_update(void)
sku_overwrite_mapping[oem_index].dc_loadline[i];
}
}
+
+void variant_final(void)
+{
+ uint32_t sku_id = variant_board_sku();
+
+ switch (sku_id) {
+ case SKU_0_BARD:
+ case SKU_1_BARD:
+ case SKU_2_BARD:
+ case SKU_3_BARD:
+ case SKU_4_BARD:
+ case SKU_5_BARD:
+ case SKU_6_BARD:
+ case SKU_7_BARD:
+ case SKU_0_EKKO:
+ case SKU_1_EKKO:
+ case SKU_2_EKKO:
+ case SKU_3_EKKO:
+ case SKU_4_EKKO:
+ case SKU_5_EKKO:
+ case SKU_6_EKKO:
+ case SKU_7_EKKO:
+ /* Enable FPMCU late in the boot process to achieve
+ * ~150ms of power off time in total.
+ */
+ gpio_output(GPP_B11, 1); /* PCH_FP_PWR_EN */
+ mdelay(3);
+ gpio_output(GPP_C9, 1); /* FP_RST_ODL */
+ break;
+ default:
+ break;
+ }
+}