diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2021-07-23 12:50:12 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-29 09:13:56 +0000 |
| commit | cf35fd37482f750fffb087920185c05f95031f1b (patch) | |
| tree | 1cd23e11b942b3fa5ad58d309e5a9ccc7c47a94b /src/mainboard | |
| parent | c2f85c6aafb00b779f222d19a02144889059268c (diff) | |
mb/siemens/mc_ehl1: Disable L1 substates for PCIe root ports
L1 substates of a PCIe link are meant to save some power when the link
is not active but have the drawback that the PCIe latency is increased
as PLLs are switched on and off as needed.
In order to get a better realtime performance, disable all substates for
every PCIe root port.
Change-Id: Ic5bc8410709d0f0094810bc11a7723e88c30e397
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 1eece7aeed..d1c5c82b2e 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -69,6 +69,14 @@ chip soc/intel/elkhartlake register "PcieClkSrcClkReq[4]" = "0xFF" register "PcieClkSrcClkReq[5]" = "0xFF" + # Disable all L1 substates for PCIe root ports + register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[3]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[5]" = "L1_SS_DISABLED" + # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" |