diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-09-25 18:43:02 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-09-25 18:43:02 +0000 |
| commit | 88f55b2c12f94fd0451902ee2edc663f12e401f4 (patch) | |
| tree | 446179d449934a1dafeb2a2df44b8a515e380807 /src/mainboard | |
| parent | 6bb3bdf869ab06a972520c5a58c6fc9b7cfe99f4 (diff) | |
some progress on kconfig:
- northbridges are done
- southbridges are done
- Intel CPUs are done, with a design that the board only has to specify
the socket it has, and the CPUs are pulled in automatically. There is
some more cleanup possible in that area, but I'll do that later
- a couple more mainboards compile:
- intel/eagleheights
- intel/jarrell
- intel/mtarvon
- intel/truxton
- intel/xe7501devkit
- sunw/ultra40
- supermicro/h8dme
- tyan/s2850
- tyan/s2875
- via/epia
- via/epia-cn
- via/epia-m
- via/epia-m700
- via/epia-n
- via/pc2500e
(PPC not considered, probably overlooked something)
All of them only _build_, but some options are probably completely
wrong. To be fixed later
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
39 files changed, 1487 insertions, 13 deletions
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 88de40421b..a7bada779f 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -441,5 +441,14 @@ config COREBOOT_ROMSIZE_KB help Map the config names to an integer. +config ROM_SIZE + hex + default 0x20000 if COREBOOT_ROMSIZE_KB_128 + default 0x40000 if COREBOOT_ROMSIZE_KB_256 + default 0x80000 if COREBOOT_ROMSIZE_KB_512 + default 0x100000 if COREBOOT_ROMSIZE_KB_1024 + default 0x200000 if COREBOOT_ROMSIZE_KB_2048 + default 0x400000 if COREBOOT_ROMSIZE_KB_4096 + endmenu diff --git a/src/mainboard/Makefile.romccboard.inc b/src/mainboard/Makefile.romccboard.inc index 1fcf43e3b1..b95a0cb35b 100644 --- a/src/mainboard/Makefile.romccboard.inc +++ b/src/mainboard/Makefile.romccboard.inc @@ -44,15 +44,17 @@ obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o ifdef POST_EVALUATION +ROMCCFLAGS ?= -mcpu=p2 + $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c - $(obj)/romcc -mcpu=p2 -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ + $(obj)/romcc -mcpu=$(ROMCCFLAGS) -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ ifeq ($(CONFIG_HAVE_OPTION_TABLE),y) $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h - $(obj)/romcc -mcpu=p2 -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + $(obj)/romcc -mcpu=$(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ else $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c - $(obj)/romcc -mcpu=p2 -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + $(obj)/romcc -mcpu=$(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ endif endif diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig index 792d600548..c14e88c8ad 100644 --- a/src/mainboard/intel/Kconfig +++ b/src/mainboard/intel/Kconfig @@ -1 +1,12 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_INTEL + +source "src/mainboard/intel/eagleheights/Kconfig" +source "src/mainboard/intel/jarrell/Kconfig" +source "src/mainboard/intel/mtarvon/Kconfig" +source "src/mainboard/intel/truxton/Kconfig" +source "src/mainboard/intel/xe7501devkit/Kconfig" + +endchoice + diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig new file mode 100644 index 0000000000..92e9a382b6 --- /dev/null +++ b/src/mainboard/intel/eagleheights/Kconfig @@ -0,0 +1,48 @@ +config BOARD_INTEL_EAGLEHEIGHTS + bool "EagleHeights" + select ARCH_X86 + select CPU_INTEL_SOCKET_BGA956 + select NORTHBRIDGE_INTEL_I3100 + select SOUTHBRIDGE_INTEL_I3100 + select SUPERIO_INTEL_I3100 + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select HAVE_HIGH_TABLES + select MMCONF_SUPPORT + select USE_PRINTK_IN_CAR + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + select AP_IN_SIPI_WAIT + help + Intel EagleHeights mainboard. + +config MAINBOARD_DIR + string + default intel/eagleheights + depends on BOARD_INTEL_EAGLEHEIGHTS + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + depends on BOARD_INTEL_EAGLEHEIGHTS + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_INTEL_EAGLEHEIGHTS + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_INTEL_EAGLEHEIGHTS + +config LB_CKS_LOC + int + default 123 + depends on BOARD_INTEL_EAGLEHEIGHTS + +config MAINBOARD_PART_NUMBER + string + default "EagleHeights" + depends on BOARD_INTEL_EAGLEHEIGHTS + diff --git a/src/mainboard/intel/eagleheights/Makefile.inc b/src/mainboard/intel/eagleheights/Makefile.inc new file mode 100644 index 0000000000..1f9c31f5eb --- /dev/null +++ b/src/mainboard/intel/eagleheights/Makefile.inc @@ -0,0 +1,38 @@ +driver-y += mainboard.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-y += reset.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS=\ + -DCONFIG_MMCONF_SUPPORT=1 \ + -DCONFIG_MMCONF_BASE_ADDRESS=0xe0000000 + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + diff --git a/src/mainboard/intel/eagleheights/devicetree.cb b/src/mainboard/intel/eagleheights/devicetree.cb new file mode 100644 index 0000000000..e5bbf20297 --- /dev/null +++ b/src/mainboard/intel/eagleheights/devicetree.cb @@ -0,0 +1,73 @@ +chip northbridge/intel/i3100 + device pci_domain 0 on + device pci 00.0 on end # IMCH + device pci 00.1 on end # IMCH error status + device pci 01.0 on end # IMCH EDMA engine + device pci 02.0 on end # PCIe port A/A0 + device pci 03.0 on end # PCIe port A1 + chip southbridge/intel/i3100 + # PIRQ line -> legacy IRQ mappings + register "pirq_a_d" = "0x8b808a8a" + register "pirq_e_h" = "0x85808080" + + device pci 1c.0 on end # PCIe port B0 + device pci 1c.1 off end # PCIe port B1 + device pci 1c.2 off end # PCIe port B2 + device pci 1c.3 off end # PCIe port B3 + device pci 1d.0 on end # USB (UHCI) 1 + device pci 1d.1 on end # USB (UHCI) 2 + device pci 1d.7 on end # USB (EHCI) + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/intel/i3100 + device pnp 4e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + chip superio/smsc/smscsuperio + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.2 off # Serial Port 4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 2 + end + device pnp 2e.4 off # Serial Port 3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.7 on # PS/2 Keyboard / Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 2e.a off # Runtime registers + io 0x60 = 0x600 + end + end + end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + device pci 1f.4 on end # Performance counters + end + end + device apic_cluster 0 on + chip cpu/intel/bga956 + device apic 0 on end + end + end +end + diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig new file mode 100644 index 0000000000..8cfa632acf --- /dev/null +++ b/src/mainboard/intel/jarrell/Kconfig @@ -0,0 +1,33 @@ +config BOARD_INTEL_JARRELL + bool "Jarrell" + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7520 + select SOUTHBRIDGE_INTEL_PXHD + select SOUTHBRIDGE_INTEL_I82801ER + select SUPERIO_NSC_PC87427 + select HAVE_PIRQ_TABLE + select UDELAY_TSC + help + Intel Jarrell mainboard. + +config MAINBOARD_DIR + string + default intel/jarrell + depends on BOARD_INTEL_JARRELL + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_INTEL_JARRELL + +config LB_CKS_LOC + int + default 123 + depends on BOARD_INTEL_JARRELL + +config MAINBOARD_PART_NUMBER + string + default "Jarrell" + depends on BOARD_INTEL_JARRELL + diff --git a/src/mainboard/intel/jarrell/Makefile.inc b/src/mainboard/intel/jarrell/Makefile.inc new file mode 100644 index 0000000000..7d098f978d --- /dev/null +++ b/src/mainboard/intel/jarrell/Makefile.inc @@ -0,0 +1,4 @@ +obj-y += reset.o +ROMCCFLAGS := -mcpu=p4 +include $(src)/mainboard/Makefile.romccboard.inc + diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig new file mode 100644 index 0000000000..255ddc393d --- /dev/null +++ b/src/mainboard/intel/mtarvon/Kconfig @@ -0,0 +1,41 @@ +config BOARD_INTEL_MTARVON + bool "Mt. Arvon" + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA479M + select NORTHBRIDGE_INTEL_I3100 + select SOUTHBRIDGE_INTEL_I3100 + select SUPERIO_INTEL_I3100 + select HAVE_PIRQ_TABLE + select UDELAY_TSC + help + Intel Mt. Arvon mainboard. + +config MAINBOARD_DIR + string + default intel/mtarvon + depends on BOARD_INTEL_MTARVON + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_INTEL_MTARVON + +config LB_CKS_LOC + int + default 123 + depends on BOARD_INTEL_MTARVON + +config MAINBOARD_PART_NUMBER + string + default "Mt. Arvon" + depends on BOARD_INTEL_MTARVON + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_INTEL_MTARVON + +config IRQ_SLOT_COUNT + int + default 1 + depends on BOARD_INTEL_MTARVON diff --git a/src/mainboard/intel/mtarvon/Makefile.inc b/src/mainboard/intel/mtarvon/Makefile.inc new file mode 100644 index 0000000000..a6be734529 --- /dev/null +++ b/src/mainboard/intel/mtarvon/Makefile.inc @@ -0,0 +1,3 @@ +ROMCCFLAGS := -mcpu=p4 +include $(src)/mainboard/Makefile.romccboard.inc + diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig new file mode 100644 index 0000000000..490db9d240 --- /dev/null +++ b/src/mainboard/intel/truxton/Kconfig @@ -0,0 +1,43 @@ +config BOARD_INTEL_TRUXTON + bool "Truxton" + select ARCH_X86 + select CPU_INTEL_EP80579 + select NORTHBRIDGE_INTEL_I3100 + select SOUTHBRIDGE_INTEL_I3100 + select SUPERIO_INTEL_I3100 + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select UDELAY_TSC + help + Intel Truxton mainboard. + +config MAINBOARD_DIR + string + default intel/truxton + depends on BOARD_INTEL_TRUXTON + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_INTEL_TRUXTON + +config LB_CKS_LOC + int + default 123 + depends on BOARD_INTEL_TRUXTON + +config MAINBOARD_PART_NUMBER + string + default "Truxton" + depends on BOARD_INTEL_TRUXTON + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_INTEL_TRUXTON + +config IRQ_SLOT_COUNT + int + default 1 + depends on BOARD_INTEL_TRUXTON + diff --git a/src/mainboard/intel/truxton/Makefile.inc b/src/mainboard/intel/truxton/Makefile.inc new file mode 100644 index 0000000000..59c6b14fa7 --- /dev/null +++ b/src/mainboard/intel/truxton/Makefile.inc @@ -0,0 +1,3 @@ +ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi +include $(src)/mainboard/Makefile.romccboard.inc + diff --git a/src/mainboard/intel/xe7501devkit/Kconfig b/src/mainboard/intel/xe7501devkit/Kconfig new file mode 100644 index 0000000000..db4dbd3305 --- /dev/null +++ b/src/mainboard/intel/xe7501devkit/Kconfig @@ -0,0 +1,47 @@ +config BOARD_INTEL_XE7501DEVKIT + bool "xe7501 DevKit" + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7501 + select SOUTHBRIDGE_INTEL_I82870 + select SOUTHBRIDGE_INTEL_I82801CA + select SUPERIO_SMSC_LPC47B272 + select HAVE_PIRQ_TABLE + select UDELAY_TSC + help + Intel xe7501 devkit mainboard. + +config MAINBOARD_DIR + string + default intel/xe7501devkit + depends on BOARD_INTEL_XE7501DEVKIT + +config LB_CKS_RANGE_START + int + default 128 + depends on BOARD_INTEL_XE7501DEVKIT + +config LB_CKS_RANGE_END + int + default 130 + depends on BOARD_INTEL_XE7501DEVKIT + +config LB_CKS_LOC + int + default 131 + depends on BOARD_INTEL_XE7501DEVKIT + +config MAINBOARD_PART_NUMBER + string + default "EIDXE7501DEVKIT" + depends on BOARD_INTEL_XE7501DEVKIT + +config HAVE_OPTION_TABLE + bool + default y + depends on BOARD_INTEL_XE7501DEVKIT + +config IRQ_SLOT_COUNT + int + default 12 + depends on BOARD_INTEL_XE7501DEVKIT diff --git a/src/mainboard/intel/xe7501devkit/Makefile.inc b/src/mainboard/intel/xe7501devkit/Makefile.inc new file mode 100644 index 0000000000..a064b3dd46 --- /dev/null +++ b/src/mainboard/intel/xe7501devkit/Makefile.inc @@ -0,0 +1,13 @@ +ROMCCFLAGS := -mcpu=p4 +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +ifeq ($(CONFIG_PCI_ROM_RUN),y) + ifeq ($(CONFIG_PCI_ROM_RUN),y) + obj-y += vgarom.o + else + obj-y += no_vgarom.o + endif +else + obj-y += no_vgarom.o +endif +include $(src)/mainboard/Makefile.romccboard.inc + diff --git a/src/mainboard/sunw/Kconfig b/src/mainboard/sunw/Kconfig index 792d600548..b04d9053c0 100644 --- a/src/mainboard/sunw/Kconfig +++ b/src/mainboard/sunw/Kconfig @@ -1 +1,8 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_SUNW + +source "src/mainboard/sunw/ultra40/Kconfig" + +endchoice + diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig new file mode 100644 index 0000000000..8cdd1f7da9 --- /dev/null +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -0,0 +1,130 @@ +config BOARD_SUNW_ULTRA40 + bool "Ultra40" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_CK804 + select SUPERIO_SMSC_LPC47M10X + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + help + Sun Ultra40. + +config MAINBOARD_DIR + string + default sunw/ultra40 + depends on BOARD_SUNW_ULTRA40 + +config DCACHE_RAM_BASE + hex + default 0xcf000 + depends on BOARD_SUNW_ULTRA40 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + depends on BOARD_SUNW_ULTRA40 + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_SUNW_ULTRA40 + +config HAVE_HARD_RESET + bool + default y + depends on BOARD_SUNW_ULTRA40 + +config IOAPIC + bool + default y + depends on BOARD_SUNW_ULTRA40 + +config K8_REV_F_SUPPORT + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUNW_ULTRA40 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_SUNW_ULTRA40 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_SUNW_ULTRA40 + +config MAINBOARD_PART_NUMBER + string + default "ultra40" + depends on BOARD_SUNW_ULTRA40 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_SUNW_ULTRA40 + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config MAX_CPUS + int + default 4 + depends on BOARD_SUNW_ULTRA40 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_SUNW_ULTRA40 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUNW_ULTRA40 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUNW_ULTRA40 + +config USE_INIT + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUNW_ULTRA40 + +config CONSOLE_VGA + bool + default y + depends on BOARD_SUNW_ULTRA40 + +config PCI_ROM_RUN + bool + default y + depends on BOARD_SUNW_ULTRA40 + diff --git a/src/mainboard/sunw/ultra40/Makefile.inc b/src/mainboard/sunw/ultra40/Makefile.inc new file mode 100644 index 0000000000..39f12d34c8 --- /dev/null +++ b/src/mainboard/sunw/ultra40/Makefile.inc @@ -0,0 +1,81 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS=\ + -DCONFIG_AP_IN_SIPI_WAIT=0 \ + -DCONFIG_USE_PRINTK_IN_CAR=1 \ + -DCONFIG_HAVE_HIGH_TABLES=1 + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig index 792d600548..9c984985c2 100644 --- a/src/mainboard/supermicro/Kconfig +++ b/src/mainboard/supermicro/Kconfig @@ -1 +1,14 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_SUPERMICRO + +source "src/mainboard/supermicro/h8dme/Kconfig" +#source "src/mainboard/supermicro/h8dmr/Kconfig" +#source "src/mainboard/supermicro/x6dai_g/Kconfig" +#source "src/mainboard/supermicro/x6dhe_g/Kconfig" +#source "src/mainboard/supermicro/x6dhe_g2/Kconfig" +#source "src/mainboard/supermicro/x6dhr_ig/Kconfig" +#source "src/mainboard/supermicro/x6dhr_ig2/Kconfig" + +endchoice + diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig new file mode 100644 index 0000000000..c3e857a367 --- /dev/null +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -0,0 +1,130 @@ +config BOARD_SUPERMICRO_H8DME + bool "h8dme" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_F + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_MCP55 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + help + h8dme + +config MAINBOARD_DIR + string + default supermicro/h8dme + depends on BOARD_SUPERMICRO_H8DME + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_SUPERMICRO_H8DME + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_SUPERMICRO_H8DME + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_SUPERMICRO_H8DME + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_SUPERMICRO_H8DME + +config HAVE_HARD_RESET + bool + default y + depends on BOARD_SUPERMICRO_H8DME + +config IOAPIC + bool + default y + depends on BOARD_SUPERMICRO_H8DME + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUPERMICRO_H8DME + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_SUPERMICRO_H8DME + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_SUPERMICRO_H8DME + +config LB_CKS_LOC + int + default 123 + depends on BOARD_SUPERMICRO_H8DME + +config MAINBOARD_PART_NUMBER + string + default "ultra40" + depends on BOARD_SUPERMICRO_H8DME + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_SUPERMICRO_H8DME + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_SUPERMICRO_H8DME + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_SUPERMICRO_H8DME + +config MAX_CPUS + int + default 4 + depends on BOARD_SUPERMICRO_H8DME + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_SUPERMICRO_H8DME + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUPERMICRO_H8DME + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUPERMICRO_H8DME + +config USE_INIT + bool + default n + depends on BOARD_SUPERMICRO_H8DME + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUPERMICRO_H8DME + +config CONSOLE_VGA + bool + default y + depends on BOARD_SUPERMICRO_H8DME + +config PCI_ROM_RUN + bool + default y + depends on BOARD_SUPERMICRO_H8DME + diff --git a/src/mainboard/supermicro/h8dme/Makefile.inc b/src/mainboard/supermicro/h8dme/Makefile.inc new file mode 100644 index 0000000000..e51ef68290 --- /dev/null +++ b/src/mainboard/supermicro/h8dme/Makefile.inc @@ -0,0 +1,82 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o +driver-y += ../../../drivers/i2c/i2cmux2/i2cmux2.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS=\ + -DCONFIG_AP_IN_SIPI_WAIT=0 \ + -DCONFIG_USE_PRINTK_IN_CAR=1 \ + -DCONFIG_HAVE_HIGH_TABLES=1 + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + diff --git a/src/mainboard/tyan/s2850/Kconfig b/src/mainboard/tyan/s2850/Kconfig new file mode 100644 index 0000000000..6ae7f0ec95 --- /dev/null +++ b/src/mainboard/tyan/s2850/Kconfig @@ -0,0 +1,65 @@ +config BOARD_TYAN_S2850 + bool "Tyan S2850" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8111 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default tyan/s2850 + depends on BOARD_TYAN_S2850 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TYAN_S2850 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TYAN_S2850 + +config MAINBOARD_PART_NUMBER + string + default "s2850" + depends on BOARD_TYAN_S2850 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2850 + depends on BOARD_TYAN_S2850 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_TYAN_S2850 + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_TYAN_S2850 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2850 + +config MAX_CPUS + int + default 2 + depends on BOARD_TYAN_S2850 + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_TYAN_S2850 + +config USE_INIT + bool + default n + depends on BOARD_TYAN_S2850 diff --git a/src/mainboard/tyan/s2850/Makefile.inc b/src/mainboard/tyan/s2850/Makefile.inc new file mode 100644 index 0000000000..88582f5329 --- /dev/null +++ b/src/mainboard/tyan/s2850/Makefile.inc @@ -0,0 +1 @@ +include $(src)/mainboard/tyan/Makefile.s289x.inc diff --git a/src/mainboard/tyan/s2875/Kconfig b/src/mainboard/tyan/s2875/Kconfig new file mode 100644 index 0000000000..57e3bab1c9 --- /dev/null +++ b/src/mainboard/tyan/s2875/Kconfig @@ -0,0 +1,71 @@ +config BOARD_TYAN_S2875 + bool "Tyan S2875" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8151 + select SOUTHBRIDGE_AMD_AMD8111 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default tyan/s2875 + depends on BOARD_TYAN_S2875 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TYAN_S2875 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TYAN_S2875 + +config MAINBOARD_PART_NUMBER + string + default "s2875" + depends on BOARD_TYAN_S2875 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2875 + depends on BOARD_TYAN_S2875 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_TYAN_S2875 + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_TYAN_S2875 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2875 + +config MAX_CPUS + int + default 4 + depends on BOARD_TYAN_S2875 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_TYAN_S2875 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_TYAN_S2875 + +config USE_INIT + bool + default n + depends on BOARD_TYAN_S2875 diff --git a/src/mainboard/tyan/s2875/Makefile.inc b/src/mainboard/tyan/s2875/Makefile.inc new file mode 100644 index 0000000000..88582f5329 --- /dev/null +++ b/src/mainboard/tyan/s2875/Makefile.inc @@ -0,0 +1 @@ +include $(src)/mainboard/tyan/Makefile.s289x.inc diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig index 787b32bc56..8f2d0db12d 100644 --- a/src/mainboard/via/Kconfig +++ b/src/mainboard/via/Kconfig @@ -2,8 +2,13 @@ choice prompt "Mainboard model" depends on VENDOR_VIA -source "src/mainboard/via/vt8454c/Kconfig" +source "src/mainboard/via/epia/Kconfig" +source "src/mainboard/via/epia-cn/Kconfig" +source "src/mainboard/via/epia-m/Kconfig" +source "src/mainboard/via/epia-m700/Kconfig" source "src/mainboard/via/epia-n/Kconfig" +source "src/mainboard/via/pc2500e/Kconfig" +source "src/mainboard/via/vt8454c/Kconfig" endchoice diff --git a/src/mainboard/via/epia-cn/Kconfig b/src/mainboard/via/epia-cn/Kconfig new file mode 100644 index 0000000000..6d57e15895 --- /dev/null +++ b/src/mainboard/via/epia-cn/Kconfig @@ -0,0 +1,45 @@ +config BOARD_VIA_EPIA_CN + bool "EPIA-CN" + select ARCH_X86 + select CPU_VIA_C7 + select NORTHBRIDGE_VIA_CN700 + select SOUTHBRIDGE_VIA_VT8237R + select SUPERIO_VIA_VT1211 + select HAVE_PIRQ_TABLE + help + VIA EPIA-CN mainboard. + +config MAINBOARD_DIR + string + default via/epia-cn + depends on BOARD_VIA_EPIA_CN + +#config DCACHE_RAM_BASE +# hex +# default 0xffef0000 +# depends on BOARD_VIA_EPIA_CN +# +#config DCACHE_RAM_SIZE +# hex +# default 0x8000 +# depends on BOARD_VIA_EPIA_CN + +config MAINBOARD_PART_NUMBER + string + default "EPIA_CN" + depends on BOARD_VIA_EPIA_CN + +config VIDEO_MB + int + default 32 + depends on BOARD_VIA_EPIA_CN + +config RAMBASE + hex + default 0x4000 + depends on BOARD_VIA_EPIA_CN + +config IRQ_SLOT_COUNT + int + default 9 + depends on BOARD_VIA_EPIA_CN diff --git a/src/mainboard/via/epia-cn/Makefile.inc b/src/mainboard/via/epia-cn/Makefile.inc new file mode 100644 index 0000000000..a6c8073117 --- /dev/null +++ b/src/mainboard/via/epia-cn/Makefile.inc @@ -0,0 +1,63 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +initobj-y += crt0.o +obj-y += mainboard.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o + +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc +crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc +crt0-y += auto.inc +crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS= + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + diff --git a/src/mainboard/via/epia-m/Kconfig b/src/mainboard/via/epia-m/Kconfig new file mode 100644 index 0000000000..865b8294ec --- /dev/null +++ b/src/mainboard/via/epia-m/Kconfig @@ -0,0 +1,41 @@ +config BOARD_VIA_EPIA_M + bool "EPIA-M" + select ARCH_X86 + select CPU_VIA_C3 + select NORTHBRIDGE_VIA_VT8623 + select SOUTHBRIDGE_VIA_VT8235 + select SOUTHBRIDGE_RICOH_RL5C476 + select SUPERIO_VIA_VT1211 + select HAVE_PIRQ_TABLE + help + VIA EPIA-M mainboard. + +config MAINBOARD_DIR + string + default via/epia-m + depends on BOARD_VIA_EPIA_M + +#config DCACHE_RAM_BASE +# hex +# default 0xffef0000 +# depends on BOARD_VIA_EPIA_M + +#config DCACHE_RAM_SIZE +# hex +# default 0x8000 +# depends on BOARD_VIA_EPIA_M + +config MAINBOARD_PART_NUMBER + string + default "EPIA_M" + depends on BOARD_VIA_EPIA_M + +config RAMBASE + hex + default 0x4000 + depends on BOARD_VIA_EPIA_M + +config IRQ_SLOT_COUNT + int + default 5 + depends on BOARD_VIA_EPIA_M diff --git a/src/mainboard/via/epia-m/Makefile.inc b/src/mainboard/via/epia-m/Makefile.inc new file mode 100644 index 0000000000..08d9f07920 --- /dev/null +++ b/src/mainboard/via/epia-m/Makefile.inc @@ -0,0 +1,65 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +initobj-y += crt0.o +obj-y += mainboard.o +obj-y += vgabios.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/northbridge/via/vx800/romstrap.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/northbridge/via/vx800/romstrap.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc +crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc +crt0-y += auto.inc +crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS= + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + diff --git a/src/mainboard/via/epia-m/auto.c b/src/mainboard/via/epia-m/auto.c index 8fdfce3399..5a93aa7541 100644 --- a/src/mainboard/via/epia-m/auto.c +++ b/src/mainboard/via/epia-m/auto.c @@ -20,7 +20,7 @@ /* */ -void udelay(int usecs) +void udelay(unsigned usecs) { int i; for(i = 0; i < usecs; i++) diff --git a/src/mainboard/via/epia-m700/Kconfig b/src/mainboard/via/epia-m700/Kconfig new file mode 100644 index 0000000000..7191d9cc60 --- /dev/null +++ b/src/mainboard/via/epia-m700/Kconfig @@ -0,0 +1,44 @@ +config BOARD_VIA_EPIA_M700 + bool "EPIA-M700" + select ARCH_X86 + select CPU_VIA_C7 + select NORTHBRIDGE_VIA_VX800 + select SUPERIO_WINBOND_W83697HF + select HAVE_PIRQ_TABLE + help + VIA EPIA-M700 mainboard. + +config MAINBOARD_DIR + string + default via/epia-m700 + depends on BOARD_VIA_EPIA_M700 + +config DCACHE_RAM_BASE + hex + default 0xffef0000 + depends on BOARD_VIA_EPIA_M700 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_VIA_EPIA_M700 + +config MAINBOARD_PART_NUMBER + string + default "EPIA_M700" + depends on BOARD_VIA_EPIA_M700 + +config VIDEO_MB + int + default 64 + depends on BOARD_VIA_EPIA_M700 + +config RAMBASE + hex + default 0x4000 + depends on BOARD_VIA_EPIA_M700 + +config IRQ_SLOT_COUNT + int + default 13 + depends on BOARD_VIA_EPIA_M700 diff --git a/src/mainboard/via/epia-m700/Makefile.inc b/src/mainboard/via/epia-m700/Makefile.inc new file mode 100644 index 0000000000..2b43fcd137 --- /dev/null +++ b/src/mainboard/via/epia-m700/Makefile.inc @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +initobj-y += crt0.o +obj-y += mainboard.o +obj-y += wakeup.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o + +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/northbridge/via/vx800/romstrap.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/northbridge/via/vx800/romstrap.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/via/car/cache_as_ram.inc +crt0-y += cache_as_ram_auto.inc + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS= + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + diff --git a/src/mainboard/via/epia-n/Kconfig b/src/mainboard/via/epia-n/Kconfig index d3e4d2f074..17d101f704 100644 --- a/src/mainboard/via/epia-n/Kconfig +++ b/src/mainboard/via/epia-n/Kconfig @@ -6,7 +6,6 @@ config BOARD_VIA_EPIA_N select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_WINBOND_W83697HF select HAVE_PIRQ_TABLE - select USE_PRINTK_IN_CAR help VIA EPIA-N mainboard. diff --git a/src/mainboard/via/epia-n/Makefile.inc b/src/mainboard/via/epia-n/Makefile.inc index a100d9ac31..f5429fa286 100644 --- a/src/mainboard/via/epia-n/Makefile.inc +++ b/src/mainboard/via/epia-n/Makefile.inc @@ -44,9 +44,7 @@ crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc ifdef POST_EVALUATION -MAINBOARD_OPTIONS=\ - -DCONFIG_USE_PRINTK_IN_CAR=1 \ - -DCONFIG_HAVE_HIGH_TABLES=1 +MAINBOARD_OPTIONS= $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ diff --git a/src/mainboard/via/epia/Kconfig b/src/mainboard/via/epia/Kconfig new file mode 100644 index 0000000000..2e7468e5a6 --- /dev/null +++ b/src/mainboard/via/epia/Kconfig @@ -0,0 +1,35 @@ +config BOARD_VIA_EPIA + bool "EPIA" + select ARCH_X86 + select CPU_VIA_C3 + select NORTHBRIDGE_VIA_VT8601 + select SOUTHBRIDGE_VIA_VT8231 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + help + VIA EPIA mainboard. + +config MAINBOARD_DIR + string + default via/epia + depends on BOARD_VIA_EPIA + +#config DCACHE_RAM_BASE +# hex +# default 0xffef0000 +# depends on BOARD_VIA_EPIA +# +#config DCACHE_RAM_SIZE +# hex +# default 0x8000 +# depends on BOARD_VIA_EPIA + +config MAINBOARD_PART_NUMBER + string + default "EPIA" + depends on BOARD_VIA_EPIA + +config RAMBASE + hex + default 0x4000 + depends on BOARD_VIA_EPIA diff --git a/src/mainboard/via/epia/Makefile.inc b/src/mainboard/via/epia/Makefile.inc new file mode 100644 index 0000000000..6acb251b23 --- /dev/null +++ b/src/mainboard/via/epia/Makefile.inc @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +initobj-y += crt0.o +obj-y += mainboard.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc +crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc +crt0-y += auto.inc +crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS= + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + diff --git a/src/mainboard/via/epia/auto.c b/src/mainboard/via/epia/auto.c index d10fec9563..e490402ba0 100644 --- a/src/mainboard/via/epia/auto.c +++ b/src/mainboard/via/epia/auto.c @@ -16,7 +16,7 @@ /* */ -void udelay(int usecs) +void udelay(unsigned usecs) { int i; for (i = 0; i < usecs; i++) diff --git a/src/mainboard/via/pc2500e/Kconfig b/src/mainboard/via/pc2500e/Kconfig new file mode 100644 index 0000000000..be33783fae --- /dev/null +++ b/src/mainboard/via/pc2500e/Kconfig @@ -0,0 +1,45 @@ +config BOARD_VIA_PC2500E + bool "PC2500E" + select ARCH_X86 + select CPU_VIA_C7 + select NORTHBRIDGE_VIA_CN700 + select SOUTHBRIDGE_VIA_VT8237R + select SUPERIO_ITE_IT8716F + select HAVE_PIRQ_TABLE + help + VIA PC2500E mainboard. + +config MAINBOARD_DIR + string + default via/pc2500e + depends on BOARD_VIA_PC2500E + +#config DCACHE_RAM_BASE +# hex +# default 0xffef0000 +# depends on BOARD_VIA_PC2500E +# +#config DCACHE_RAM_SIZE +# hex +# default 0x8000 +# depends on BOARD_VIA_PC2500E + +config MAINBOARD_PART_NUMBER + string + default "PC2500E" + depends on BOARD_VIA_PC2500E + +config VIDEO_MB + int + default 32 + depends on BOARD_VIA_PC2500E + +config RAMBASE + hex + default 0x4000 + depends on BOARD_VIA_PC2500E + +config IRQ_SLOT_COUNT + int + default 10 + depends on BOARD_VIA_PC2500E diff --git a/src/mainboard/via/pc2500e/Makefile.inc b/src/mainboard/via/pc2500e/Makefile.inc new file mode 100644 index 0000000000..a6c8073117 --- /dev/null +++ b/src/mainboard/via/pc2500e/Makefile.inc @@ -0,0 +1,63 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +initobj-y += crt0.o +obj-y += mainboard.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o + +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc +crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc +crt0-y += auto.inc +crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS= + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + |