soc/intel/tigerlake: Update chip files

Update chip files to include :
  - Update chip.c based on TGL FSP
  - Update chip.h based on TGL FSP
  - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update
  - Update pmc_utils.c and JSL devicetree for build failure

Reference
PCH EDS#576591 vol1 rev1.2

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 3 insertions, 3 deletions

diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index b4ed69744b..854df4656b 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -8,9 +8,9 @@ chip soc/intel/tigerlake
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE
 	# offset bits also need to be changed.
-	register "gpe0_dw0" = "GPP_B"
-	register "gpe0_dw1" = "GPP_D"
-	register "gpe0_dw2" = "GPP_E"
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw2" = "GPP_E"
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"