diff options
| author | Ren Kuo <ren.kuo@quanta.corp-partner.google.com> | 2024-09-11 13:49:29 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-09-16 14:13:38 +0000 |
| commit | 19788920cb64695f85baaea3248d7844bae11b93 (patch) | |
| tree | e66861014f5f5b2f49f57a071ab5e38ff1983308 /src/mainboard | |
| parent | fa5e3d9d4474e50758ddf2287d26b164806c597c (diff) | |
mb/google/brox/jubilant: Update cpu power limit settings
1)Modify jubilant cpu power limit setting depend on the brox
baseboad settgins,refer to CL:
https://review.coreboot.org/c/coreboot/+/83752
2)Update PL1,PL2, and PL4 value from jubilant thermal design
PL1 = 15W
PL2 = 41W
PL4 = 87W
BUG=b:364441688
BRANCH=None
TEST=Able to successfully boot on jubilant photo SKU1 and SKU2
boards with AC w/o battery.
Test on AC 65W and 45W w/o battery,and check the PL values.
Change-Id: I9a143d9faaa6c57b0d314c0ff6c0e55f556d7216
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brox/variants/jubilant/overridetree.cb | 6 | ||||
| -rw-r--r-- | src/mainboard/google/brox/variants/jubilant/ramstage.c | 31 |
2 files changed, 16 insertions, 21 deletions
diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index b88e959637..48cc783077 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -75,6 +75,12 @@ chip soc/intel/alderlake }, }" + register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 41, + .tdp_pl4 = 87, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf diff --git a/src/mainboard/google/brox/variants/jubilant/ramstage.c b/src/mainboard/google/brox/variants/jubilant/ramstage.c index 86418da2ad..0f78e26bd0 100644 --- a/src/mainboard/google/brox/variants/jubilant/ramstage.c +++ b/src/mainboard/google/brox/variants/jubilant/ramstage.c @@ -15,33 +15,23 @@ const struct cpu_power_limits performance_efficient_limits[] = { { .mchid = PCI_DID_INTEL_RPL_P_ID_3, .cpu_tdp = 15, - .pl1_min_power = 6000, - .pl1_max_power = 15000, - .pl2_min_power = 55000, - .pl2_max_power = 55000, - .pl4_power = 114000 + .pl1_min_power = 15000, + .pl1_max_power = 18000, + .pl2_min_power = 41000, + .pl2_max_power = 41000, + .pl4_power = 87000 }, { .mchid = PCI_DID_INTEL_RPL_P_ID_4, .cpu_tdp = 15, - .pl1_min_power = 6000, - .pl1_max_power = 15000, - .pl2_min_power = 55000, - .pl2_max_power = 55000, - .pl4_power = 114000 + .pl1_min_power = 15000, + .pl1_max_power = 18000, + .pl2_min_power = 41000, + .pl2_max_power = 41000, + .pl4_power = 87000 }, }; -const struct system_power_limits sys_limits[] = { - /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ - { PCI_DID_INTEL_RPL_P_ID_3, 15, 60 }, - { PCI_DID_INTEL_RPL_P_ID_4, 15, 60 }, -}; - -const struct psys_config psys_config = { - .efficiency = 86, -}; - void __weak variant_devtree_update(void) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); @@ -50,5 +40,4 @@ void __weak variant_devtree_update(void) size_t limits_size = ARRAY_SIZE(performance_efficient_limits); variant_update_power_limits(limits, limits_size); - variant_update_psys_power_limits(limits, sys_limits, limits_size, &psys_config); } |