summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorBrandon Breitenstein <brandon.breitenstein@intel.com>2020-03-11 14:07:23 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-30 08:40:45 +0000
commitfc932374a2860addbdf00dc3bd141b556508b8f3 (patch)
tree3baf68b290d99f9cd580140475b0d0d70948eb5e /src/mainboard
parentbc8373830128ff2991c1a8e9ff3e4255deefe746 (diff)
soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3
FSP UPD TcssAuxOri is used for setting the IOM_TYPEC_SW_CONFIGURATION_3. Configure TcssAuxOri to retimer enabled on the port 2 Type-C port. This setting informs the SoC that a retimer is taking care of SBU orientation therefore it does not need to do any flipping. The IOM_TYPEC_SW_CONFIGURATION_3 is a bitfield that controls the aux orientation settings for the Type-C ports. The TGL EDS describes this setting and what each bit represents. Reference section 3.6.5 in TGL EDS #575681 BUG=b:145943811 BRANCH=none TEST=Boot to OS and check Type-C port1 Display on volteer, Connecting Type-C display should work regardless of Type-C cable orientation. Change-Id: Iae356113cbdc72983f800060b1ebebe3c66b9daf Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39459 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
0 files changed, 0 insertions, 0 deletions