binaryPI: Disable CAR with empty stack

Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.

While we still preserve cache contents (there is wbinvd deep
inside AMD_DISABLE_STACK macro), we now actually do a stack
switch and much more closely meet the specification of CAR
teardown sequence in AGESA specifications.

We now somewhat incorrectly include files from agesa/ tree,
but the whole agesawrapper.c file removal will address the
issue of overall directory layout.

Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

6 files changed, 26 insertions, 72 deletions

diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 29cd8a7284..eefae85337 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -20,6 +20,7 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
@@ -28,9 +29,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* Must come first to enable PCI MMCONF. */
-	amd_initmmio();
-
 	hudson_lpc_port80();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -62,18 +60,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x40);
 	AGESAWRAPPER(amdinitpost);
+}
+
+void agesa_postcar(struct sysinfo *cb)
+{
 	post_code(0x41);
 	AGESAWRAPPER(amdinitenv);
-	/* TODO: Disable cache is not ok. */
-	disable_cache_as_ram();
 
 	if (acpi_is_wakeup_s4()) {
 		outb(0xEE, PM_INDEX);
 		outb(0x8, PM_DATA);
 	}
-
-	post_code(0x50);
-	copy_and_run();
-
-	post_code(0x54);  /* Should never see this post code. */
 }
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index 0ba1c1dfea..4da974796b 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -25,6 +25,7 @@
 #include <console/console.h>
 #include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
@@ -32,11 +33,7 @@
 #include <southbridge/amd/pi/hudson/hudson.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	u32 val;
-
-	/* Must come first to enable PCI MMCONF. */
-	amd_initmmio();
+{	u32 val;
 
 	/*
 	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
@@ -78,19 +75,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x40);
 	AGESAWRAPPER(amdinitpost);
+}
 
+void agesa_postcar(struct sysinfo *cb)
+{
 	post_code(0x41);
 	AGESAWRAPPER(amdinitenv);
-	/*
-	  If code hangs here, please check cahaltasm.S
-	*/
-	disable_cache_as_ram();
 
 	outb(0xEA, 0xCD6);
 	outb(0x1, 0xcd7);
-
-	post_code(0x50);
-	copy_and_run();
-
-	post_code(0x54);  /* Should never see this post code. */
 }
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 5530a25e84..bbd5ad0528 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -25,6 +25,7 @@
 #include <console/console.h>
 #include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
@@ -40,9 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* Must come first to enable PCI MMCONF. */
-	amd_initmmio();
-
 	/*
 	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
 	 *  LpcClk[1:0]".  This following register setting has been
@@ -89,16 +87,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x40);
 	AGESAWRAPPER(amdinitpost);
+}
 
+void agesa_postcar(struct sysinfo *cb)
+{
 	post_code(0x41);
 	AGESAWRAPPER(amdinitenv);
-	/*
-	  If code hangs here, please check cahaltasm.S
-	*/
-	disable_cache_as_ram();
-
-	post_code(0x50);
-	copy_and_run();
-
-	post_code(0x54);  /* Should never see this post code. */
 }
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index c98ae25bc0..ff2c4c411d 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -25,6 +25,7 @@
 #include <console/console.h>
 #include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
@@ -35,9 +36,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* Must come first to enable PCI MMCONF. */
-	amd_initmmio();
-
 	/*
 	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
 	 *  LpcClk[1:0]".  This following register setting has been
@@ -88,20 +86,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x40);
 	AGESAWRAPPER(amdinitpost);
+}
 
+void agesa_postcar(struct sysinfo *cb)
+{
 	//PspMboxBiosCmdDramInfo();
 	post_code(0x41);
 	AGESAWRAPPER(amdinitenv);
-	/*
-	  If code hangs here, please check cahaltasm.S
-	*/
-	disable_cache_as_ram();
 
 	outb(0xEA, 0xCD6);
 	outb(0x1, 0xcd7);
-
-	post_code(0x50);
-	copy_and_run();
-
-	post_code(0x54);  /* Should never see this post code. */
 }
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c
index d8342c917f..576a3eefbb 100644
--- a/src/mainboard/bap/ode_e21XX/romstage.c
+++ b/src/mainboard/bap/ode_e21XX/romstage.c
@@ -25,6 +25,7 @@
 #include <console/console.h>
 #include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
@@ -39,9 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* Must come first to enable PCI MMCONF. */
-	amd_initmmio();
-
 	/*
 	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
 	 *  LpcClk[1:0]".  This following register setting has been
@@ -82,20 +80,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x40);
 	AGESAWRAPPER(amdinitpost);
+}
 
+void agesa_postcar(struct sysinfo *cb)
+{
 	//PspMboxBiosCmdDramInfo();
 	post_code(0x41);
 	AGESAWRAPPER(amdinitenv);
-	/*
-	  If code hangs here, please check cahaltasm.S
-	*/
-	disable_cache_as_ram();
 
 	outb(0xEA, 0xCD6);
 	outb(0x1, 0xcd7);
-
-	post_code(0x50);
-	copy_and_run();
-
-	post_code(0x54);  /* Should never see this post code. */
 }
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index c95adb6555..1ccf7c4e36 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -25,6 +25,7 @@
 #include <console/console.h>
 #include <commonlib/loglevel.h>
 #include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
@@ -52,8 +53,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	outb(0xD2, 0xcd6);
 	outb(0x00, 0xcd7);
 
-	amd_initmmio();
-
 	hudson_lpc_port80();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -85,27 +84,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x40);
 	AGESAWRAPPER(amdinitpost);
+}
 
+void agesa_postcar(struct sysinfo *cb)
+{
 	//PspMboxBiosCmdDramInfo();
 	post_code(0x41);
 	AGESAWRAPPER(amdinitenv);
-	/*
-	  If code hangs here, please check cahaltasm.S
-	*/
-	disable_cache_as_ram();
 
 	init_tpm(false);
 
 	outb(0xEA, 0xCD6);
 	outb(0x1, 0xcd7);
-
-	post_code(0x50);
-	copy_and_run();
-
-	post_code(0x54);  /* Should never see this post code. */
 }
 
-
 static void early_lpc_init(void)
 {
 	u32 setting = 0x0;