armv7/exynos/snow: new cache maintenance API

This adds a new API for cache maintenance operations. The idea is
to be more explicit about operations that are going on so it's easier
to manage branch predictor, cache, and TLB cleans and invalidations.

Also, this adds some operations that were missing but required early
on, such as branch predictor invalidation. Instruction and sync
barriers were wrong earlier as well since the imported API assumed
we compield with -march=armv5 (which we don't) and was missing
wrappers for the native ARMv7 ISB/DSB/DMB instructions.

For now, this is a start and it gives us something we can easily use
in libpayload for doing things like cleaning and invalidating dcache
when doing DMA transfers.

TODO:
- Set cache policy explicitly before re-enabling. Right now it's left
  at default.
- Finish deprecating old cache maintenance API.
- We do an extra icache/dcache flush when going from bootblock to
  romstage.

Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2729
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 4 insertions, 22 deletions

diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index ea2feec782..bfb4156b68 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -18,12 +18,12 @@
  */
 
 #include <types.h>
-#include <system.h>
 
-#include <cache.h>
+#include <armv7.h>
 #include <cbfs.h>
 #include <common.h>
 
+#include <arch/cache.h>
 #include <arch/gpio.h>
 #include <cpu/samsung/exynos5250/clk.h>
 #include <cpu/samsung/exynos5250/dmc.h>
@@ -52,20 +52,6 @@ static int board_wakeup_permitted(void)
 }
 #endif
 
-/*
- * Set/clear program flow prediction and return the previous state.
- */
-static int config_branch_prediction(int set_cr_z)
-{
-	unsigned int cr;
-
-	/* System Control Register: 11th bit Z Branch prediction enable */
-	cr = get_cr();
-	set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
-
-	return cr & CR_Z;
-}
-
 static void initialize_s5p_mshc(void)
 {
 	/* MMC0: Fixed, 8 bit mode, connected with GPIO. */
@@ -95,10 +81,6 @@ void main(void)
 	int ret;
 	void *entry;
 
-	/* FIXME: if we boot from USB, we need to disable branch prediction
-	 * before copying from USB into RAM */
-	config_branch_prediction(1);
-
 	clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
 
 	/* Clock must be initialized before console_init, otherwise you may need
@@ -108,7 +90,6 @@ void main(void)
 	system_clock_init(mem, arm_ratios);
 
 	console_init();
-
 	/*
 	 * FIXME: Do necessary I2C init so low-level PMIC code doesn't need to.
 	 * Also, we should only call power_init() on cold boot.
@@ -132,7 +113,8 @@ void main(void)
 		while(1);
 	}
 
-	mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB);
+	/* Set up MMU and caches */
+	mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB);
 
 	initialize_s5p_mshc();