diff options
| author | Peter Lemenkov <lemenkov@gmail.com> | 2019-11-30 21:12:22 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-10 14:45:51 +0000 |
| commit | 4b59fe402a6b76ada3792abf5dec95d144d1c9e9 (patch) | |
| tree | 4dcb03ef6c7f23b172279ee6a36ecafae3a0cd6c /src/mainboard | |
| parent | 9e81aacd9c8c840e1b881b09844e90774c7441cd (diff) | |
mb/lenovo/x1/devicetree: Use subsystemid inheritance
Change-Id: I0081b5f219447b110dddfa82cbae51d9ca282f5b
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37384
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/lenovo/x220/variants/x1/overridetree.cb | 48 |
1 files changed, 13 insertions, 35 deletions
diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb index 54f6485d25..a08a12f588 100644 --- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb @@ -13,12 +13,10 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x13121312" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21e8 - end # host bridge - device pci 02.0 on - subsystemid 0x17aa 0x21e8 - end # vga controller + subsystemid 0x17aa 0x21e8 inherit + + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # Enable SATA ports 0 (HDD bay) & 2 (msata) & 3 (esatap) @@ -26,37 +24,23 @@ chip northbridge/intel/sandybridge # X1 does not have ExpressCard slot register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - device pci 1a.0 on - subsystemid 0x17aa 0x21e8 - end # USB2 EHCI #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21e8 - end # High Definition Audio + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21e8 - end # PCIe Port #2 (wlan) + device pci 1c.1 on end # PCIe Port #2 (wlan) device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 on - subsystemid 0x17aa 0x21e8 chip drivers/ricoh/rce822 # Ricoh cardreader - device pci 00.0 on - subsystemid 0x17aa 0x21e8 - end + device pci 00.0 on end end end # PCIe Port #5 (SD) device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on - subsystemid 0x17aa 0x21e8 - end # PCIe Port #7 + device pci 1c.6 on end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21e8 - end # USB2 EHCI #1 + device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on #LPC bridge - subsystemid 0x17aa 0x21e8 chip ec/lenovo/h8 register "config2" = "0xe0" register "config3" = "0xc0" @@ -71,15 +55,9 @@ chip northbridge/intel/sandybridge register "has_bdc_detection" = "0" end end # LPC bridge - device pci 1f.2 on - subsystemid 0x17aa 0x21e8 - end # SATA Controller 1 - device pci 1f.3 on - subsystemid 0x17aa 0x21e8 - end # SMBus - device pci 1f.6 on - subsystemid 0x17aa 0x21e8 - end # Thermal + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal end end end |