diff options
| author | Richard Spiegel <richard.spiegel@silverbackltd.com> | 2017-11-20 12:30:32 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-22 18:28:29 +0000 |
| commit | 2983c708155466d88776338b3a7faec9f80f0134 (patch) | |
| tree | 75341bbfdcc37f1a2b91d15b952aaf16b056a5bf /src/mainboard | |
| parent | db7b8afc912d28cc368b89f86435f2c8a6e11cf1 (diff) | |
Create SOC description file soc.asl
Request from commit 519680948b (move carrizo_fch.asl code to soc), merge
several includes into a single file in soc directory.
Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl.
Then copy the required section from dsdt.asl into a new soc.asl.
Affected boards: amd/gardenia and google/kahlee.
BUG=b:69368752
Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22541
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/amd/gardenia/dsdt.asl | 17 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/dsdt.asl | 17 |
2 files changed, 6 insertions, 28 deletions
diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index bc81602747..e6acfc8bbc 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -61,19 +61,8 @@ DefinitionBlock ( Name(_STA, 0x0B) } - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <fch.asl> - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <pci_int.asl> - - /* Describe the devices in the Southbridge */ - #include <soc_fch.asl> + /* Describe the SOC */ + #include <soc.asl> } /* End \_SB scope */ diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index 885dd8dce0..ded0dc8779 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -61,19 +61,8 @@ DefinitionBlock ( Name(_UID, 0xAA) } - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <fch.asl> - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <pci_int.asl> - - /* Describe the devices in the Southbridge */ - #include <soc_fch.asl> + /* Describe the SOC */ + #include <soc.asl> } /* End \_SB scope */ |