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authorRonak Kanabar <ronak.kanabar@intel.com>2020-04-02 16:03:41 +0530
committerNico Huber <nico.h@gmx.de>2020-04-06 11:06:53 +0000
commitb6a523927d58c13b7a0bf6c8d20ef29a43e1aa95 (patch)
tree8cdbb813ff1738d61a1d22de58462ebc08488bf1 /src/mainboard
parente8d483923baed00fbc16de38e6532f4cc27cdc9b (diff)
soc/intel/jasperlake: Remove DDI A lane programming
For newer Intel graphics (>=11), the DDI port max lanes default to 4. And kernel driver no longer relies on coreboot to provide information via DDI_BUF_CTL_A (for DDI port A) register programming. Hence removing this code. BUG=b:150788968 BRANCH=None TEST=checked jslrvp compilation and boot. Change-Id: I4c171ec6a57d6fc53bee88420bfb3c0fbc5dc057 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40038 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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