diff options
| author | Morris Hsu <morris-hsu@quanta.corp-partner.google.com> | 2024-08-09 14:53:20 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-11 17:34:31 +0000 |
| commit | 5bc6bd4c41591b9b322436519275dfadd5096474 (patch) | |
| tree | 22f0eea463a25db0ad99e2490a467b192481f5a4 /src/mainboard | |
| parent | ffc1cbb8fcc234cc46ea47121f189d4490117204 (diff) | |
mb/google/brox/jubilant: update overridetree for dptf settings
Update dptf settings for EVT.
BUG=None
TEST=emerge-brox coreboot chromeos-bootiamge
Change-Id: Iadc95c14da6f879e25dac4804907e340dc16e47f
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83842
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brox/variants/jubilant/overridetree.cb | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index d4deb92eca..4110f437da 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -41,8 +41,9 @@ chip soc/intel/alderlake device ref dtt on chip drivers/intel/dptf ## sensor information - register "options.tsr[0].desc" = ""DRAM_SOC"" - register "options.tsr[1].desc" = ""Fan-Inlet"" + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Soc"" + register "options.tsr[2].desc" = ""Charger"" ## Active Policy register "policies.active" = "{ @@ -101,7 +102,7 @@ chip soc/intel/alderlake register "controls.power_limits" = "{ .pl1 = { .min_power = 15000, - .max_power = 15000, + .max_power = 18000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, |