diff options
| author | Yidi Lin <yidilin@chromium.org> | 2024-08-28 17:15:36 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-09-02 09:16:59 +0000 |
| commit | 3d5ff65b273c5bd1fcfcef478869d20661a23470 (patch) | |
| tree | 404d7544dfe822e2768b8d906ffd6e3a9483dbae /src/mainboard | |
| parent | cea84e2536976581223e83fead847582694fe471 (diff) | |
mb/google/cherry: Complete PCIe reset in romstage
De-assert PERST# at romstage to reduce the waiting time in ramstage.
Before
```
[INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries)
```
After
```
[INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST#
[DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST#
[INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries)
```
BUG=none
TEST=boot from NVMe
Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84118
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/cherry/romstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c index f375867c28..ab05220121 100644 --- a/src/mainboard/google/cherry/romstage.c +++ b/src/mainboard/google/cherry/romstage.c @@ -8,6 +8,7 @@ #include <soc/mt6315.h> #include <soc/mt6359p.h> #include <soc/mt6360.h> +#include <soc/pcie.h> #include <soc/pll_common.h> #include <soc/pmif.h> #include <soc/rtc.h> @@ -33,6 +34,8 @@ void platform_romstage_main(void) mt6360_init(I2C7); clk_buf_init(); rtc_boot(); + if (CONFIG(PCI)) + mtk_pcie_deassert_perst(); mtk_dram_init(); scp_rsi_enable(); } |