mb/intel/jasperlake_rvp: Configure GPIO for JSLRVP

We need to configure GSPI related gpios for external EC and TPM.
Along with GSPI configuring gpios for LAN (power down), FSP_INT
and PCH_INT.

BUG=None
BRANCH=None
TEST=External EC card works and LAN is powered down.

Change-Id: I1f2d32537b56802d0631a94590a6ebe156c5cdd0
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40362
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 47 insertions, 3 deletions

diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig
index 82e57490e5..a1283bda48 100644
--- a/src/mainboard/intel/jasperlake_rvp/Kconfig
+++ b/src/mainboard/intel/jasperlake_rvp/Kconfig
@@ -63,4 +63,7 @@ config UART_FOR_CONSOLE
 	default 2 if INTEL_LPSS_UART_FOR_CONSOLE
 	default 0
 
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 45  # GPE0_DW1_13 (GPP_H13)
 endif
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index 7dc45ae520..cb3d1f3598 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -9,7 +9,7 @@ chip soc/intel/jasperlake
 	# route. i.e. If this route changes then the affected GPE
 	# offset bits also need to be changed.
 	register "pmc_gpe0_dw0" = "GPP_B"
-	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw1" = "GPP_H"
 	register "pmc_gpe0_dw2" = "GPP_E"
 
 	# FSP configuration
@@ -297,7 +297,7 @@ chip soc/intel/jasperlake
 			chip drivers/spi/acpi
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
 				register "compat_string" = ""google,cr50""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H13_IRQ)"
 				device spi 0 on end
 			end
 		end # GSPI #1
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
index 68f57ffd60..9b86839119 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
@@ -18,12 +18,30 @@ static const struct pad_config gpio_table[] = {
 	/* M.2_WLAN_PERST_N */
 	PAD_CFG_GPO(GPP_B17, 1, PLTRST),
 
+	/* GSPI1_CS# */
+	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+
+	/* GSPI1_CLK */
+	PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+
+	/* GSPI1_MISO */
+	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+
+	/* GSPI1_MOSI */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
+
+	/*PCH_INT_ODL*/
+	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
+
 	/* WWAN_PERST_N */
 	PAD_CFG_GPO(GPP_C0, 0, PLTRST),
 
 	/* M2_WWAN_SSD_SKT2_CFG2 */
 	PAD_CFG_GPI(GPP_C3, NONE, PLTRST),
 
+	/*SLP_LAN_N*/
+	PAD_CFG_GPO(GPP_C7, 0, PLTRST),
+
 	/* I2C0_SDA */
 	PAD_CFG_NF(GPP_C16, UP_2K, DEEP, NF1),
 
@@ -36,18 +54,27 @@ static const struct pad_config gpio_table[] = {
 	/* BT_RF_KILL_N */
 	PAD_CFG_GPO(GPP_D1, 1, PLTRST),
 
+	/*LAN_RST_N*/
+	PAD_CFG_GPO(GPP_D6, 1, PLTRST),
+
 	/* I2S_MCLK */
 	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
 
 	/* WWAN_FCP_OFF_N */
 	PAD_CFG_GPO(GPP_E3, 1, PLTRST),
 
+	/*FPS_INT*/
+	PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, INVERT),
+
 	/* WWAN EN GPIO */
 	PAD_CFG_GPO(GPP_H7, 1, PLTRST),
 
 	/* M.2_BT_I2S2_SCLK */
 	PAD_CFG_GPI(GPP_H11, NONE, PLTRST),
 
+	/*PCH_INT_ODL*/
+	PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),
+
 	/* M.2_BT_I2S2_RXD */
 	PAD_CFG_GPI(GPP_H14, NONE, PLTRST),
 
@@ -100,7 +127,21 @@ static const struct pad_config gpio_table[] = {
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
-	/* ToDo: Fill early gpio configurations for TPM */
+
+	/* GSPI1_CS# */
+	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+
+	/* GSPI1_CLK */
+	PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+
+	/* GSPI1_MISO */
+	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+
+	/* GSPI1_MOSI */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
+
+	/*PCH_INT_ODL*/
+	PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)