diff options
| author | Joseph Smith <joe@settoplinux.org> | 2010-01-29 19:15:10 +0000 |
|---|---|---|
| committer | Joseph Smith <joe@smittys.pointclark.net> | 2010-01-29 19:15:10 +0000 |
| commit | 89e45773a977da2c996221b74aef06596d345211 (patch) | |
| tree | 1a2cd556600ac4f6add469ee48fc28c06d6ffe5e /src/mainboard/thomson | |
| parent | 6bba29f84a725c67f548290bb3a9832c793797cc (diff) | |
RCA RM4100 and Thomson IP1000 auto.c rework.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/thomson')
| -rw-r--r-- | src/mainboard/thomson/ip1000/auto.c | 55 |
1 files changed, 34 insertions, 21 deletions
diff --git a/src/mainboard/thomson/ip1000/auto.c b/src/mainboard/thomson/ip1000/auto.c index 328b95203d..89454b37d7 100644 --- a/src/mainboard/thomson/ip1000/auto.c +++ b/src/mainboard/thomson/ip1000/auto.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> + * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -45,7 +45,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" -#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c" /** * The onboard 64MB PC133 memory does not have a SPD EEPROM so the @@ -73,18 +72,33 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /** - * The AC'97 Audio Controller I/O space registers are read only by default - * so we need to enable them by setting register 0x41 to 0x01. + * Setup mainboard specific registers pre raminit. */ -static void ac97_io_enable(void) +static void mb_early_setup(void) { - device_t dev; - - /* Set the ac97 audio device staticly. */ - dev = PCI_DEV(0x0, 0x1f, 0x5); - - /* Enable access to the IO space. */ - pci_write_config8(dev, 0x41, 0x01); + /* - Hub Interface to PCI Bridge Registers - */ + /* 12-Clock Retry Enable */ + pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402); + /* Master Latency Timer Count */ + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + /* I/O Address Base */ + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0); + + /* - LPC Interface Bridge Registers - */ + /* Delayed Transaction Enable */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002); + /* Disable the TCO Timer system reboot feature */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02); + /* CPU Frequency Strap */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02); + /* ACPI base address and enable Resource Indicator */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1)); + /* Enable the SMBUS */ + enable_smbus(); + /* ACPI base address and disable Resource Indicator */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR)); + /* ACPI Enable */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } static void main(unsigned long bist) @@ -102,19 +116,20 @@ static void main(unsigned long bist) hard_reset(); } - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + /* Set southbridge and superio gpios */ mb_gpio_init(); + + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - enable_smbus(); - - /* Prevent the TCO timer from rebooting us */ - i82801xx_halt_tco_timer(); - /* Halt if there was a built in self test failure. */ report_bist_failure(bist); + /* Setup mainboard specific registers */ + mb_early_setup(); + + /* SDRAM init */ sdram_set_registers(memctrl); sdram_set_spd_registers(memctrl); sdram_enable(0, memctrl); @@ -122,6 +137,4 @@ static void main(unsigned long bist) /* Check RAM. */ /* ram_check(0, 640 * 1024); */ /* ram_check(64512 * 1024, 65536 * 1024); */ - - ac97_io_enable(); -} +}
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