mb/system76/gaze15/dt: Make use of chipset devicetree

Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.

Change-Id: I290fcfdd7b2cff61c4f6cd153133c5205c6fd6d1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>

3 files changed, 19 insertions, 64 deletions

diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
index f80c45c0ba..47e9b3c920 100644
--- a/src/mainboard/system76/gaze15/devicetree.cb
+++ b/src/mainboard/system76/gaze15/devicetree.cb
@@ -52,23 +52,19 @@ chip soc/intel/cannonlake
 	device cpu_cluster 0 on end
 
 	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 01.0 on      # GPU Port
+		device ref peg0		on
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
 		end
-		device pci 02.0 on      # Integrated Graphics Device
+		device ref igpu		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device pci 04.0 on      # SA Thermal device
+		device ref dptf		on
 			register "Device4Enable" = "1"
 		end
-		device pci 12.0 on  end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 13.0 off end # Integrated Sensor Hub
-		device pci 14.0 on      # USB xHCI
+		device ref thermal	on	end
+		device ref xhci		on
 			register "usb2_ports" = "{
 				[0] = USB2_PORT_MID(OC_SKIP),		/* USB 3 Right */
 				[1] = USB2_PORT_MID(OC_SKIP),		/* USB 3 Left */
@@ -85,39 +81,22 @@ chip soc/intel/cannonlake
 				[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* Type-C */
 			}"
 		end
-		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.2 on  end # Shared SRAM
-		device pci 14.3 on      # CNVi wifi
+		device ref shared_sram	on	end
+		device ref cnvi_wifi	on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
 				device generic 0 on end
 			end
 		end
-		device pci 14.5 off end # SDCard
-		device pci 15.1 on  end # I2C #1
-		device pci 15.2 off end # I2C #2
-		device pci 15.3 off end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 on      # SATA
+		device ref i2c1		on	end
+		device ref sata		on
 			register "SataPortsEnable" = "{
 				[1] = 1, /* SSD (SATA1A) */
 				[4] = 1, /* HDD (SATA4) */
 			}"
 		end
-		device pci 19.0 off end # I2C #4
-		device pci 19.1 off end # I2C #5
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 off end # eMMC
-		device pci 1b.0 off end # PCI Express Port 17
-		device pci 1b.1 off end # PCI Express Port 18
-		device pci 1b.2 off end # PCI Express Port 19
-		device pci 1b.3 off end # PCI Express Port 20
-		device pci 1b.4 on      # PCI Express Port 21
+		device ref uart2	on	end
+		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 11 (SSD2)
 			register "PcieRpEnable[20]" = "1"
 			register "PcieRpLtrEnable[20]" = "1"
@@ -125,18 +104,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcClkReq[11]" = "11"
 			register "PcieRpSlotImplemented[20]" = "1"
 		end
-		device pci 1b.5 off end # PCI Express Port 22
-		device pci 1b.6 off end # PCI Express Port 23
-		device pci 1b.7 off end # PCI Express Port 24
-		device pci 1c.0 off end # PCI Express Port 1
-		device pci 1c.1 off end # PCI Express Port 2
-		device pci 1c.2 off end # PCI Express Port 3
-		device pci 1c.3 off end # PCI Express Port 4
-		device pci 1c.4 off end # PCI Express Port 5
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on      # PCI Express Port 9
+		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 10 (SSD)
 			register "PcieRpEnable[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "1"
@@ -144,11 +112,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcClkReq[10]" = "10"
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 on      # PCI Express Port 14
+		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 6 (WLAN)
 			register "PcieRpEnable[13]" = "1"
 			register "PcieRpLtrEnable[13]" = "1"
@@ -156,7 +120,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcClkReq[6]" = "6"
 			register "PcieRpSlotImplemented[13]" = "1"
 		end
-		device pci 1d.6 on      # PCI Express Port 15
+		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 5 (LAN)
 			register "PcieRpEnable[14]" = "1"
 			register "PcieRpLtrEnable[14]" = "1"
@@ -164,12 +128,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcClkReq[5]" = "5"
 			register "PcieRpSlotImplemented[14]" = "1"
 		end
-		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1e.0 off end # UART #0
-		device pci 1e.1 off end # UART #1
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 off end # GSPI #1
-		device pci 1f.0 on      # LPC Interface
+		device ref lpc_espi	on
 			register "gen1_dec" = "0x00040069"
 			register "gen2_dec" = "0x00fc0e01"
 			register "gen3_dec" = "0x00fc0f01"
@@ -177,15 +136,11 @@ chip soc/intel/cannonlake
 				device pnp 0c31.0 on end
 			end
 		end
-		device pci 1f.1 off end # P2SB
-		device pci 1f.2 hidden end # Power Management Controller
-		device pci 1f.3 on      # Intel HDA
+		device ref hda		on
 			register "PchHdaAudioLinkHda" = "1"
 			register "PchHdaAudioLinkDmic0" = "1"
 			register "PchHdaAudioLinkDmic1" = "1"
 		end
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 off end # GbE
+		device ref smbus	on	end
 	end
 end
diff --git a/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb b/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb
index e94d703a19..824c5af32d 100644
--- a/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb
+++ b/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb
@@ -11,7 +11,7 @@ chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x8550 inherit
 
-		device pci 15.0 on      # I2C0
+		device ref i2c0	on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA1202""
 				register "generic.desc" = ""Synaptics Touchpad""
diff --git a/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb b/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb
index 02275df10b..bb7c8f16a4 100644
--- a/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb
+++ b/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb
@@ -11,7 +11,7 @@ chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x8520 inherit
 
-		device pci 15.0 on      # I2C0
+		device ref i2c0	on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ELAN0412""
 				register "generic.desc" = ""ELAN Touchpad""