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authorAngel Pons <th3fanbus@gmail.com>2021-02-19 16:02:45 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-03-05 10:55:58 +0000
commit81e9263caabb7735f01f61d046c3c4df91badcab (patch)
treec96e0efe8507cc62c9b6b1e16cac27bcb7423fb9 /src/mainboard/system76/oryp5
parente4606bbff79ef1b0771417a1ee4e3bb0fb1909c2 (diff)
soc/intel/apollolake: Add `GPE0_STS_BIT` macro
The datasheet indicates that this bit is reserved. However, subsequent patches need to use this macro in common code, or else builds fail. To iron out this difference, mask out the bit in `soc_get_smi_status`, so that common code always sees it as zero. Finally, add an entry for the bit in `smi_sts_bits` for debugging usage, noting that it is reserved. Change-Id: Ib4408e016ba29cf8f7b125c95bfa668136b9eb93 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/system76/oryp5')
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