mb/intel/ehlcrb: Add initial mainboard code

This is a initial mainboard code cloned entirely from jasperlake_rvp
aimed to serve as base for further mainboard check-ins.

This patch is based on TGL_upstream series patches:
https://review.coreboot.org/c/coreboot/+/37868

List of changes on top off initial jasperlake_rvp clone:
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jslrvp" with "ehlcrb"
4. Remove unwanted SPD file, add empty SPD as placeholder
6. Empty romstage_fsp_params.c, to fill it later with SOC specific
   config
7. Empty GPIO configurations, to be filled as per board
8. Empty memory.c configurations, to be filled as per board
9. Add board support namely BOARD_INTEL_ELKHARTLAKE_CRB
10. Replace jslrvp variant with ehlcrb variant

Changes to follow on top of this:
 1. Add correct memory parameters, add SPDs
 2. Clean up devicetree as per tigerlake SOC
 3. Add GPIO support
 4. Update ehl fmd file to replace 32MB chromeos.fmd

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I2cbe9f12468318680b148739edec5222582e42a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

0 files changed, 0 insertions, 0 deletions