diff options
| author | Tim Crawford <tcrawford@system76.com> | 2022-01-07 14:12:34 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-25 18:05:35 +0000 |
| commit | 2a404b599b3385b3246a2ee20844d2bc7a428035 (patch) | |
| tree | 64541bbb7f407c3c8e2615240e5454a67c4d0b80 /src/mainboard/system76/darp7 | |
| parent | b65c3015b0c931b8ad7897a9835798cd97dbcf5b (diff) | |
mb/system76: Enable SrcClk pin for CPU PCIe RPs
This reverts commit bd9b044a96cc ("mb/system76: rtd3: Remove SrcClk pin
on CPU RP").
Previously, RTD3 expected a PCH index for the root port and did not work
with the CPU PCIe RP present on TGL, so SrcClk pin was disabled.
Set them now that RTD3 supports mapping the index for the CPU RP.
Change-Id: Ia7519b9f5a2be52cd5575615c28d20371a26996b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Diffstat (limited to 'src/mainboard/system76/darp7')
| -rw-r--r-- | src/mainboard/system76/darp7/devicetree.cb | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index 21f8141c5f..4b7ad233ea 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -113,8 +113,7 @@ chip soc/intel/tigerlake chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST# - # TODO: Support disable/enable CPU RP clock - register "srcclk_pin" = "-1" # SSD1_CLKREQ# + register "srcclk_pin" = "0" # SSD1_CLKREQ# device generic 0 on end end end |