mb/system76/cml-u: Convert lemp9 to a variant

Change-Id: I13777cf6f663ca8c52a059a60cfcdfe6ecc5b9ae
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>

12 files changed, 970 insertions, 4 deletions

diff --git a/src/mainboard/system76/cml-u/variants/darp6/gpio.c b/src/mainboard/system76/cml-u/variants/darp6/gpio.c
new file mode 100644
index 0000000000..41353a9acc
--- /dev/null
+++ b/src/mainboard/system76/cml-u/variants/darp6/gpio.c
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_NC(GPD0, NONE), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
+	PAD_NC(GPD2, NONE),
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
+	PAD_NC(GPD6, NONE),
+	PAD_CFG_GPI(GPD7, NONE, DEEP), // 100k pull up
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
+	PAD_NC(GPD9, NONE), // GPD9_RTD3
+	PAD_NC(GPD10, NONE),
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ with 10k pull up
+	PAD_CFG_GPI(GPP_A7, NONE, DEEP), // TPM_PIRQ#
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# with 8.2k pull-up
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
+	PAD_NC(GPP_A10, NONE),
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE), // PCH_GPP_A12
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
+	PAD_NC(GPP_A14, NONE),
+	PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK
+	PAD_NC(GPP_A16, NONE),
+	PAD_CFG_GPI(GPP_A17, NONE, DEEP), // LIGHT_KB_DET#
+	PAD_NC(GPP_A18, NONE),
+	PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_CFG_GPO(GPP_A22, 0, DEEP), // PS8338B_SW
+	PAD_CFG_GPO(GPP_A23, 0, DEEP), // PS8338B_PCH
+
+	/* ------- GPIO Group B ------- */
+	PAD_NC(GPP_B0, NONE), // CORE_VID0
+	PAD_NC(GPP_B1, NONE), // CORE_VID1
+	PAD_CFG_GPO(GPP_B2, 0, DEEP), // CNVI_WAKE#
+	PAD_NC(GPP_B3, NONE),
+	PAD_NC(GPP_B4, NONE),
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ#
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ#
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ#
+	PAD_NC(GPP_B11, NONE), // EXT_PWR_GATE#
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# with 100k pull down
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE), // PCH_GPP_B16
+	PAD_NC(GPP_B17, NONE), // PCH_GPP_B17
+	PAD_NC(GPP_B18, NONE), // PCH_GPP_B18 - strap for disabling no reboot mode
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE), // PCH_GPP_B22
+	PAD_NC(GPP_B23, NONE),
+
+	/* ------- GPIO Group C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT_DDR
+	PAD_NC(GPP_C2, NONE), // PCH_GPP_C2 with 4.7k pull-up
+	PAD_NC(GPP_C3, NONE),
+	PAD_NC(GPP_C4, NONE),
+	PAD_NC(GPP_C5, NONE), // PCH_GPP_C5 with 4.7k pull down
+	PAD_CFG_GPI(GPP_C6, NONE, DEEP), // LAN_WAKEUP#
+	PAD_NC(GPP_C7, NONE),
+	PAD_NC(GPP_C8, NONE),
+	_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), // TBCIO_PLUG_EVENT
+	PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST), // TBT_FRC_PWR
+	PAD_NC(GPP_C11, NONE),
+	PAD_CFG_GPO(GPP_C12, 1, PLTRST), // GPP_C12_RTD3
+	PAD_CFG_GPO(GPP_C13, 1, PLTRST), // SSD_PWR_DN#
+	PAD_CFG_GPO(GPP_C14, 0, PLTRST), // TBTA_HRESET
+	PAD_CFG_GPO(GPP_C15, 1, PLTRST), // TBT_PERST_N
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE), // SWI# on galp4, NC on darp6
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_NC(GPP_C22, NONE),
+	PAD_CFG_GPI_APIC_LOW(GPP_C23, NONE, PLTRST), // NC on galp4, TP_ATTN# on darp6
+
+	/* ------- GPIO Group D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_NC(GPP_D5, NONE),
+	PAD_NC(GPP_D6, NONE),
+	PAD_NC(GPP_D7, NONE),
+	PAD_CFG_GPO(GPP_D8, 1, DEEP), // SB_BLON
+	_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000), // SWI#
+	PAD_NC(GPP_D10, NONE),
+	_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), // RTD3_PCIE_WAKE#
+	PAD_NC(GPP_D12, NONE), // PCH_GPP_D12
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_CFG_GPO(GPP_D15, 1, DEEP), // TBT_RTD3_PWR_EN_D15 on galp4, NC on darp6
+	PAD_CFG_GPO(GPP_D16, 1, PWROK), // RTD3_3G_PW R_EN on galp4, NC on darp6
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // GPPC_DMIC_CLK
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // GPPC_DMIC_DATA
+	PAD_CFG_GPI(GPP_D21, NONE, DEEP), // TPM_DET#
+	PAD_CFG_GPI(GPP_D22, NONE, DEEP), // TPM_TCM_Detect
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group E ------- */
+	PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 with 10k pull-up
+	PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT#
+	PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), // SATAGP2
+	PAD_NC(GPP_E3, NONE),
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2
+	PAD_NC(GPP_E7, NONE),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
+	PAD_NC(GPP_E9, NONE), // GP_BSSB_CLK
+	PAD_NC(GPP_E10, NONE), // GPP_E10
+	PAD_NC(GPP_E11, NONE), // GPP_E11
+	PAD_NC(GPP_E12, NONE), // USB_OC#78
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD
+	_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI#
+	_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), // SCI#
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), // MDP_CTRLDATA
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F1, NONE),
+	PAD_NC(GPP_F2, NONE),
+	PAD_NC(GPP_F3, NONE),
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+	PAD_NC(GPP_F10, NONE),
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_NC(GPP_F18, NONE),
+	PAD_NC(GPP_F19, NONE),
+	PAD_NC(GPP_F20, NONE),
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_CFG_GPI(GPP_F23, NONE, DEEP), // A4WP_PRESENT
+
+	/* ------- GPIO Group G ------- */
+	PAD_CFG_GPI(GPP_G0, NONE, DEEP), // EDP_DET
+	PAD_NC(GPP_G1, NONE),
+	PAD_NC(GPP_G2, NONE),
+	PAD_CFG_GPO(GPP_G3, 0, DEEP), // ASM1543_I_SEL0
+	PAD_CFG_GPO(GPP_G4, 0, DEEP), // ASM1543_I_SEL1
+	PAD_NC(GPP_G5, NONE), // BOARD_ID
+	PAD_NC(GPP_G6, NONE),
+	PAD_NC(GPP_G7, NONE), // TBT_Detect
+
+	/* ------- GPIO Group H ------- */
+	PAD_NC(GPP_H0, NONE),
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), // CNVI_RST#
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_NC(GPP_H3, NONE),
+	PAD_NC(GPP_H4, NONE),
+	PAD_NC(GPP_H5, NONE),
+	PAD_NC(GPP_H6, NONE),
+	PAD_NC(GPP_H7, NONE),
+	PAD_NC(GPP_H8, NONE),
+	PAD_NC(GPP_H9, NONE),
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	PAD_NC(GPP_H14, NONE), // G_INT1
+	PAD_NC(GPP_H15, NONE),
+	PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H17, NONE),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE), // GPPC_H21
+	PAD_CFG_GPO(GPP_H22, 1, DEEP), // TBT_RTD3_PWR_EN_H22
+	PAD_NC(GPP_H23, NONE), // WIGIG_PEWAKE on galp4, NC on darp6
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
index 631803c68a..a39622cea3 100644
--- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
@@ -1,7 +1,24 @@
 chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x1404 inherit
-		device pci 15.0 on
+
+		device pci 14.0 on      # USB xHCI
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A port 1
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"		# 3G / LTE
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"		# Type-C port 3
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"		# USB Board port 4
+			register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)"		# Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"		# Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type-A port 1
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# 4G
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type-C port 3
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# USB Board port 4
+			register "usb3_ports[4]" = "USB3_PORT_EMPTY"			# Used by TBT
+			register "usb3_ports[5]" = "USB3_PORT_EMPTY"			# Used by TBT
+		end
+		device pci 15.0 on      # I2C #0
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA1202""
 				register "generic.desc" = ""Synaptics Touchpad""
@@ -10,6 +27,43 @@ chip soc/intel/cannonlake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 2c on end
 			end
-		end # I2C #0
+		end
+		device pci 17.0 on      # SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[2]" = "1"
+		end
+		device pci 1c.4 on      # PCI Express Port 5
+			# PCI Express Root port #5 x4, Clock 4 (TBT)
+			register "PcieRpEnable[4]" = "1"
+			register "PcieRpLtrEnable[4]" = "1"
+			register "PcieRpHotPlug[4]" = "1"
+			register "PcieClkSrcUsage[4]" = "4"
+			register "PcieClkSrcClkReq[4]" = "4"
+		end
+		device pci 1d.0 on      # PCI Express Port 9
+			# PCI Express Root port #9 x1, Clock 3 (LAN)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[3]" = "8"
+			register "PcieClkSrcClkReq[3]" = "3"
+		end
+		device pci 1d.1 on      # PCI Express Port 10
+			# PCI Express Root port #10 x1, Clock 2 (WLAN)
+			register "PcieRpEnable[9]" = "1"
+			register "PcieRpLtrEnable[9]" = "0"
+			register "PcieClkSrcUsage[2]" = "9"
+			register "PcieClkSrcClkReq[2]" = "2"
+		end
+		device pci 1d.4 on      # PCI Express Port 13
+			# PCI Express Root port #13 x4, Clock 5 (NVMe)
+			register "PcieRpEnable[12]" = "1"
+			register "PcieRpLtrEnable[12]" = "1"
+			register "PcieClkSrcUsage[5]" = "12"
+			register "PcieClkSrcClkReq[5]" = "5"
+		end
+		device pci 1f.3 on      # Intel HDA
+			register "PchHdaAudioLinkDmic0" = "1"
+			register "PchHdaAudioLinkDmic1" = "1"
+		end
 	end
 end
diff --git a/src/mainboard/system76/cml-u/variants/darp6/romstage.c b/src/mainboard/system76/cml-u/variants/darp6/romstage.c
new file mode 100644
index 0000000000..aae639b437
--- /dev/null
+++ b/src/mainboard/system76/cml-u/variants/darp6/romstage.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = { .spd_smbus_address = 0xa0 },
+	},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = { .spd_smbus_address = 0xa4 },
+	},
+	.rcomp_resistor = { 121, 81, 100 },
+	.rcomp_targets = { 100, 40, 20, 20, 26 },
+	.dq_pins_interleaved = 1,
+	.vref_ca_config = 2,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}
diff --git a/src/mainboard/system76/cml-u/variants/galp4/gpio.c b/src/mainboard/system76/cml-u/variants/galp4/gpio.c
new file mode 100644
index 0000000000..41353a9acc
--- /dev/null
+++ b/src/mainboard/system76/cml-u/variants/galp4/gpio.c
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_NC(GPD0, NONE), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
+	PAD_NC(GPD2, NONE),
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
+	PAD_NC(GPD6, NONE),
+	PAD_CFG_GPI(GPD7, NONE, DEEP), // 100k pull up
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
+	PAD_NC(GPD9, NONE), // GPD9_RTD3
+	PAD_NC(GPD10, NONE),
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ with 10k pull up
+	PAD_CFG_GPI(GPP_A7, NONE, DEEP), // TPM_PIRQ#
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# with 8.2k pull-up
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
+	PAD_NC(GPP_A10, NONE),
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE), // PCH_GPP_A12
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
+	PAD_NC(GPP_A14, NONE),
+	PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK
+	PAD_NC(GPP_A16, NONE),
+	PAD_CFG_GPI(GPP_A17, NONE, DEEP), // LIGHT_KB_DET#
+	PAD_NC(GPP_A18, NONE),
+	PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_CFG_GPO(GPP_A22, 0, DEEP), // PS8338B_SW
+	PAD_CFG_GPO(GPP_A23, 0, DEEP), // PS8338B_PCH
+
+	/* ------- GPIO Group B ------- */
+	PAD_NC(GPP_B0, NONE), // CORE_VID0
+	PAD_NC(GPP_B1, NONE), // CORE_VID1
+	PAD_CFG_GPO(GPP_B2, 0, DEEP), // CNVI_WAKE#
+	PAD_NC(GPP_B3, NONE),
+	PAD_NC(GPP_B4, NONE),
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ#
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ#
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ#
+	PAD_NC(GPP_B11, NONE), // EXT_PWR_GATE#
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# with 100k pull down
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE), // PCH_GPP_B16
+	PAD_NC(GPP_B17, NONE), // PCH_GPP_B17
+	PAD_NC(GPP_B18, NONE), // PCH_GPP_B18 - strap for disabling no reboot mode
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE), // PCH_GPP_B22
+	PAD_NC(GPP_B23, NONE),
+
+	/* ------- GPIO Group C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT_DDR
+	PAD_NC(GPP_C2, NONE), // PCH_GPP_C2 with 4.7k pull-up
+	PAD_NC(GPP_C3, NONE),
+	PAD_NC(GPP_C4, NONE),
+	PAD_NC(GPP_C5, NONE), // PCH_GPP_C5 with 4.7k pull down
+	PAD_CFG_GPI(GPP_C6, NONE, DEEP), // LAN_WAKEUP#
+	PAD_NC(GPP_C7, NONE),
+	PAD_NC(GPP_C8, NONE),
+	_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), // TBCIO_PLUG_EVENT
+	PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST), // TBT_FRC_PWR
+	PAD_NC(GPP_C11, NONE),
+	PAD_CFG_GPO(GPP_C12, 1, PLTRST), // GPP_C12_RTD3
+	PAD_CFG_GPO(GPP_C13, 1, PLTRST), // SSD_PWR_DN#
+	PAD_CFG_GPO(GPP_C14, 0, PLTRST), // TBTA_HRESET
+	PAD_CFG_GPO(GPP_C15, 1, PLTRST), // TBT_PERST_N
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE), // SWI# on galp4, NC on darp6
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_NC(GPP_C22, NONE),
+	PAD_CFG_GPI_APIC_LOW(GPP_C23, NONE, PLTRST), // NC on galp4, TP_ATTN# on darp6
+
+	/* ------- GPIO Group D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_NC(GPP_D5, NONE),
+	PAD_NC(GPP_D6, NONE),
+	PAD_NC(GPP_D7, NONE),
+	PAD_CFG_GPO(GPP_D8, 1, DEEP), // SB_BLON
+	_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000), // SWI#
+	PAD_NC(GPP_D10, NONE),
+	_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), // RTD3_PCIE_WAKE#
+	PAD_NC(GPP_D12, NONE), // PCH_GPP_D12
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_CFG_GPO(GPP_D15, 1, DEEP), // TBT_RTD3_PWR_EN_D15 on galp4, NC on darp6
+	PAD_CFG_GPO(GPP_D16, 1, PWROK), // RTD3_3G_PW R_EN on galp4, NC on darp6
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // GPPC_DMIC_CLK
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // GPPC_DMIC_DATA
+	PAD_CFG_GPI(GPP_D21, NONE, DEEP), // TPM_DET#
+	PAD_CFG_GPI(GPP_D22, NONE, DEEP), // TPM_TCM_Detect
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group E ------- */
+	PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 with 10k pull-up
+	PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT#
+	PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), // SATAGP2
+	PAD_NC(GPP_E3, NONE),
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2
+	PAD_NC(GPP_E7, NONE),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
+	PAD_NC(GPP_E9, NONE), // GP_BSSB_CLK
+	PAD_NC(GPP_E10, NONE), // GPP_E10
+	PAD_NC(GPP_E11, NONE), // GPP_E11
+	PAD_NC(GPP_E12, NONE), // USB_OC#78
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD
+	_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI#
+	_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), // SCI#
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), // MDP_CTRLDATA
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F1, NONE),
+	PAD_NC(GPP_F2, NONE),
+	PAD_NC(GPP_F3, NONE),
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+	PAD_NC(GPP_F10, NONE),
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_NC(GPP_F18, NONE),
+	PAD_NC(GPP_F19, NONE),
+	PAD_NC(GPP_F20, NONE),
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_CFG_GPI(GPP_F23, NONE, DEEP), // A4WP_PRESENT
+
+	/* ------- GPIO Group G ------- */
+	PAD_CFG_GPI(GPP_G0, NONE, DEEP), // EDP_DET
+	PAD_NC(GPP_G1, NONE),
+	PAD_NC(GPP_G2, NONE),
+	PAD_CFG_GPO(GPP_G3, 0, DEEP), // ASM1543_I_SEL0
+	PAD_CFG_GPO(GPP_G4, 0, DEEP), // ASM1543_I_SEL1
+	PAD_NC(GPP_G5, NONE), // BOARD_ID
+	PAD_NC(GPP_G6, NONE),
+	PAD_NC(GPP_G7, NONE), // TBT_Detect
+
+	/* ------- GPIO Group H ------- */
+	PAD_NC(GPP_H0, NONE),
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), // CNVI_RST#
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_NC(GPP_H3, NONE),
+	PAD_NC(GPP_H4, NONE),
+	PAD_NC(GPP_H5, NONE),
+	PAD_NC(GPP_H6, NONE),
+	PAD_NC(GPP_H7, NONE),
+	PAD_NC(GPP_H8, NONE),
+	PAD_NC(GPP_H9, NONE),
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	PAD_NC(GPP_H14, NONE), // G_INT1
+	PAD_NC(GPP_H15, NONE),
+	PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H17, NONE),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE), // GPPC_H21
+	PAD_CFG_GPO(GPP_H22, 1, DEEP), // TBT_RTD3_PWR_EN_H22
+	PAD_NC(GPP_H23, NONE), // WIGIG_PEWAKE on galp4, NC on darp6
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
index f6c61498be..f6be0eb358 100644
--- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
@@ -1,8 +1,62 @@
 chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x1403 inherit
-		device pci 15.0 on
+
+		device pci 14.0 on      # USB xHCI
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A port 1
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"		# 3G / LTE
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"		# Type-C port 3
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"		# USB Board port 4
+			register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)"		# Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"		# Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type-A port 1
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# 4G
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type-C port 3
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# USB Board port 4
+			register "usb3_ports[4]" = "USB3_PORT_EMPTY"			# Used by TBT
+			register "usb3_ports[5]" = "USB3_PORT_EMPTY"			# Used by TBT
+		end
+		device pci 15.0 on      # I2C #0
 			# I2C HID not supported on galp4
-		end # I2C #0
+		end
+		device pci 17.0 on      # SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[2]" = "1"
+		end
+		device pci 1c.4 on      # PCI Express Port 5
+			# PCI Express Root port #5 x4, Clock 4 (TBT)
+			register "PcieRpEnable[4]" = "1"
+			register "PcieRpLtrEnable[4]" = "1"
+			register "PcieRpHotPlug[4]" = "1"
+			register "PcieClkSrcUsage[4]" = "4"
+			register "PcieClkSrcClkReq[4]" = "4"
+		end
+		device pci 1d.0 on      # PCI Express Port 9
+			# PCI Express Root port #9 x1, Clock 3 (LAN)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[3]" = "8"
+			register "PcieClkSrcClkReq[3]" = "3"
+		end
+		device pci 1d.1 on      # PCI Express Port 10
+			# PCI Express Root port #10 x1, Clock 2 (WLAN)
+			register "PcieRpEnable[9]" = "1"
+			register "PcieRpLtrEnable[9]" = "0"
+			register "PcieClkSrcUsage[2]" = "9"
+			register "PcieClkSrcClkReq[2]" = "2"
+		end
+		device pci 1d.4 on      # PCI Express Port 13
+			# PCI Express Root port #13 x4, Clock 5 (NVMe)
+			register "PcieRpEnable[12]" = "1"
+			register "PcieRpLtrEnable[12]" = "1"
+			register "PcieClkSrcUsage[5]" = "12"
+			register "PcieClkSrcClkReq[5]" = "5"
+		end
+		device pci 1f.3 on      # Intel HDA
+			register "PchHdaAudioLinkDmic0" = "1"
+			register "PchHdaAudioLinkDmic1" = "1"
+		end
 	end
 end
diff --git a/src/mainboard/system76/cml-u/variants/galp4/romstage.c b/src/mainboard/system76/cml-u/variants/galp4/romstage.c
new file mode 100644
index 0000000000..aae639b437
--- /dev/null
+++ b/src/mainboard/system76/cml-u/variants/galp4/romstage.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = { .spd_smbus_address = 0xa0 },
+	},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = { .spd_smbus_address = 0xa4 },
+	},
+	.rcomp_resistor = { 121, 81, 100 },
+	.rcomp_targets = { 100, 40, 20, 20, 26 },
+	.dq_pins_interleaved = 1,
+	.vref_ca_config = 2,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}
diff --git a/src/mainboard/system76/cml-u/variants/lemp9/board_info.txt b/src/mainboard/system76/cml-u/variants/lemp9/board_info.txt
new file mode 100644
index 0000000000..c547c6abef
--- /dev/null
+++ b/src/mainboard/system76/cml-u/variants/lemp9/board_info.txt
@@ -0,0 +1,2 @@
+Board name: lemp9
+Release year: 2020
diff --git a/src/mainboard/system76/cml-u/variants/lemp9/data.vbt b/src/mainboard/system76/cml-u/variants/lemp9/data.vbt
new file mode 100644
index 0000000000..f14d8073e9
--- /dev/null
+++ b/src/mainboard/system76/cml-u/variants/lemp9/data.vbt
diff --git a/src/mainboard/system76/cml-u/variants/lemp9/gpio.c b/src/mainboard/system76/cml-u/variants/lemp9/gpio.c
new file mode 100644
index 0000000000..d27acadbfa
--- /dev/null
+++ b/src/mainboard/system76/cml-u/variants/lemp9/gpio.c
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_NC(GPD0, NONE),
+	PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),		/* ACPRESENT / AC_PRESENT */
+	PAD_NC(GPD2, UP_20K),
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),		/* PWRBTN# / PWR_BTN# */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),		/* SLP_S3# / SUSB#_PCH */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),		/* SLP_S4# / SUSC#_PCH */
+	PAD_NC(GPD6, UP_20K),
+	PAD_NC(GPD7, NONE),
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),		/* SUSCLK / SUS_CLK */
+	PAD_NC(GPD9, UP_20K),
+	PAD_NC(GPD10, UP_20K),
+	PAD_NC(GPD11, UP_20K),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),		/* RCIN# / SB_KBCRST# */
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),		/* LAD0 / LPC_AD0 */
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),		/* LAD1 / LPC_AD1 */
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),		/* LAD2 / LPC_AD2 */
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),		/* LAD3 / LPC_AD3 */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),		/* LFRAME# / LPC_FRAME# */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),		/* SERIRQ */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),		/* PIRQA# / TPM_PIRQ# */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),		/* CLKRUN# / PM_CLKRUN#
+							   Note: R209 is populated despite being
+							   marked no-stuff in schematic
+							 */
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),		/* CLKOUT_LPC0 / PCLK_KBC */
+	PAD_NC(GPP_A10, UP_20K),
+	PAD_NC(GPP_A11, NONE),				/* INTP_OUT (unknown and unused) */
+	PAD_NC(GPP_A12, UP_20K),
+	PAD_NC(GPP_A13, UP_20K),			/* SUSWARN#
+							   (unused due to missing DeepSx support)
+							 */
+	PAD_NC(GPP_A14, UP_20K),
+	PAD_NC(GPP_A15, UP_20K),
+	PAD_NC(GPP_A16, UP_20K),
+	PAD_NC(GPP_A17, NONE),				/* LEDKB_DET#
+							   (unused in cb; all devices of that
+							   model have KB LED)
+							 */
+	PAD_NC(GPP_A18, UP_20K),
+	PAD_NC(GPP_A19, UP_20K),
+	PAD_CFG_GPO(GPP_A20, 0, DEEP),			/* GPP_A20 / TEST_R */
+	PAD_NC(GPP_A21, UP_20K),
+	PAD_NC(GPP_A22, UP_20K),
+	PAD_NC(GPP_A23, UP_20K),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_NC(GPP_B0, UP_20K),
+	PAD_NC(GPP_B1, UP_20K),
+	PAD_NC(GPP_B2, UP_20K),				/* CNVI_WAKE#
+							   (UART_WAKE# in M.2 spec; unused)
+							 */
+	PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, PLTRST),	/* GPP_B3 (touchpad interrupt) */
+	PAD_NC(GPP_B4, UP_20K),
+	PAD_NC(GPP_B5, UP_20K),
+	PAD_NC(GPP_B6, UP_20K),
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),		/* SRCCLKREQ2# / WLAN_CLKREQ# */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),		/* SRCCLKREQ3# / CARD_CLKREQ# */
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),		/* SRCCLKREQ4# / SSD2_CLKREQ# */
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),		/* SRCCLKREQ5# / SSD1_CLKREQ# */
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),		/* SLP_S0# */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),		/* PLT_RST# */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),		/* SPKR / PCH_SPKR */
+	PAD_NC(GPP_B15, UP_20K),
+	PAD_NC(GPP_B16, UP_20K),
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, UP_20K),
+	PAD_NC(GPP_B19, UP_20K),
+	PAD_NC(GPP_B20, UP_20K),
+	PAD_NC(GPP_B21, UP_20K),
+	PAD_NC(GPP_B22, UP_20K),
+	PAD_NC(GPP_B23, UP_20K),
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),		/* SMBCLK / SMB_CLK_DDR */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),		/* SMBDATA / SMB_DAT_DDR */
+	PAD_NC(GPP_C2, UP_20K),
+	PAD_NC(GPP_C3, UP_20K),
+	PAD_NC(GPP_C4, UP_20K),
+	PAD_NC(GPP_C5, UP_20K),
+	PAD_NC(GPP_C6, UP_20K),
+	PAD_NC(GPP_C7, UP_20K),
+	PAD_NC(GPP_C8, UP_20K),
+	PAD_NC(GPP_C9, UP_20K),
+	PAD_NC(GPP_C10, UP_20K),
+	PAD_NC(GPP_C11, UP_20K),
+	PAD_NC(GPP_C12, UP_20K),
+	PAD_CFG_GPO(GPP_C13, 1, PLTRST),		/* GPP_C13 / SSD1_PWR_DN# */
+	PAD_NC(GPP_C14, UP_20K),
+	PAD_NC(GPP_C15, UP_20K),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),		/* I2C0_SDA / T_SDA */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),		/* I2C0_SCL / T_SCL */
+	PAD_NC(GPP_C18, UP_20K),
+	PAD_NC(GPP_C19, UP_20K),
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),		/* UART2_RXD */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),		/* UART2_TXD */
+	PAD_NC(GPP_C22, UP_20K),
+	PAD_NC(GPP_C23, UP_20K),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, UP_20K),
+	PAD_NC(GPP_D1, UP_20K),
+	PAD_NC(GPP_D2, UP_20K),
+	PAD_NC(GPP_D3, UP_20K),
+	PAD_NC(GPP_D4, UP_20K),
+	PAD_NC(GPP_D5, UP_20K),
+	PAD_NC(GPP_D6, UP_20K),
+	PAD_NC(GPP_D7, UP_20K),
+	PAD_CFG_GPO(GPP_D8, 1, DEEP),			/* SB_BLON */
+	PAD_CFG_GPI_SCI_LOW(GPP_D9, NONE, DEEP, LEVEL),	/* EC SWI# */
+	PAD_NC(GPP_D10, NONE),				/* DDR_TYPE_D10
+							   (unused; there is only one on-board
+							   ram type/model)
+							 */
+	PAD_NC(GPP_D11, NONE),				/* BOARD_ID
+							   (unused in cb; we already know the
+							   device model)
+							 */
+	PAD_NC(GPP_D12, UP_20K),
+	PAD_NC(GPP_D13, UP_20K),
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST),		/* SSD2_PWR_DN# */
+	PAD_NC(GPP_D15, UP_20K),
+	PAD_NC(GPP_D16, UP_20K),
+	PAD_NC(GPP_D17, UP_20K),
+	PAD_NC(GPP_D18, UP_20K),
+	PAD_NC(GPP_D19, UP_20K),
+	PAD_NC(GPP_D20, UP_20K),
+	PAD_NC(GPP_D21, NONE),				/* TPM_DET#
+							   (currently unused in cb; there seem
+							   to be no devices without TPM)
+							 */
+	PAD_NC(GPP_D22, NONE),				/* DDR_TYPE_D22
+							   (unused in cb; there is only one
+							   on-board ram type)
+							 */
+	PAD_NC(GPP_D23, UP_20K),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_NC(GPP_E0, UP_20K),
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),		/* SATAXPCIE1 / SATAGP1 */
+	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),		/* SATAXPCIE2 / SATAGP2 */
+	PAD_NC(GPP_E3, UP_20K),
+	PAD_NC(GPP_E4, UP_20K),
+	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),		/* DEVSLP1 */
+	PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),		/* DEVSLP2 */
+	PAD_NC(GPP_E7, UP_20K),
+	PAD_NC(GPP_E8, NONE),
+	PAD_NC(GPP_E9, NONE),
+	PAD_NC(GPP_E10, NONE),
+	PAD_NC(GPP_E11, NONE),
+	PAD_NC(GPP_E12, NONE),
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),		/* DDPB_HPD0 / MUX_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),		/* DDPC_HPD1 / HDMI_HPD */
+	PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE),	/* EC SMI# */
+	PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, PLTRST, LEVEL),	/* EC SCI# */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),		/* EDP_HPD */
+	PAD_NC(GPP_E18, UP_20K),
+	PAD_NC(GPP_E19, NONE),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),		/* DPPC_CTRLCLK / HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),		/* DPPC_CTRLDATA / HDMI_CTRLDATA */
+	PAD_NC(GPP_E22, UP_20K),
+	PAD_NC(GPP_E23, UP_20K),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_NC(GPP_F0, UP_20K),
+	PAD_NC(GPP_F1, UP_20K),
+	PAD_NC(GPP_F2, UP_20K),
+	PAD_NC(GPP_F3, UP_20K),
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),		/* CNV_BRI_DT / CNVI_BRI_DT */
+	PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),		/* CNV_BRI_RSP / CNVI_BRI_RSP */
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),		/* CNV_RGI_DT / CNVI_RGI_DT */
+	PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),		/* CNV_RGI_RSP / CNVI_RGI_RSP */
+	PAD_NC(GPP_F8, UP_20K),
+	PAD_NC(GPP_F9, UP_20K),
+	PAD_NC(GPP_F10, UP_20K),
+	PAD_NC(GPP_F11, UP_20K),
+	PAD_NC(GPP_F12, UP_20K),
+	PAD_NC(GPP_F13, UP_20K),
+	PAD_NC(GPP_F14, UP_20K),
+	PAD_NC(GPP_F15, UP_20K),
+	PAD_NC(GPP_F16, UP_20K),
+	PAD_NC(GPP_F17, UP_20K),
+	PAD_NC(GPP_F18, UP_20K),
+	PAD_NC(GPP_F19, UP_20K),
+	PAD_NC(GPP_F20, UP_20K),
+	PAD_NC(GPP_F21, UP_20K),
+	PAD_NC(GPP_F22, UP_20K),
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_NC(GPP_G0, UP_20K),
+	PAD_NC(GPP_G1, UP_20K),
+	PAD_NC(GPP_G2, UP_20K),
+	PAD_NC(GPP_G3, UP_20K),
+	PAD_NC(GPP_G4, UP_20K),
+	PAD_NC(GPP_G5, UP_20K),
+	PAD_NC(GPP_G6, UP_20K),
+	PAD_NC(GPP_G7, UP_20K),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, UP_20K),
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),		/* CNV_RF_RESET# / CNVI_RST# */
+	PAD_CFG_NF(GPP_H2, DN_20K, DEEP, NF3),		/* MODEM_CLKREQ / CNVI_CLKREQ */
+	PAD_NC(GPP_H3, UP_20K),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),		/* I2C2_SDA / SMD_7411 */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),		/* I2C2_SCL / SMC_7411 */
+	PAD_NC(GPP_H6, UP_20K),
+	PAD_NC(GPP_H7, UP_20K),
+	PAD_NC(GPP_H8, UP_20K),
+	PAD_NC(GPP_H9, UP_20K),
+	PAD_NC(GPP_H10, UP_20K),
+	PAD_NC(GPP_H11, UP_20K),
+	PAD_NC(GPP_H12, UP_20K),
+	PAD_NC(GPP_H13, UP_20K),
+	PAD_NC(GPP_H14, UP_20K),
+	PAD_NC(GPP_H15, UP_20K),
+	PAD_NC(GPP_H16, UP_20K),
+	PAD_NC(GPP_H17, UP_20K),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),		/* CPU_C10_GATE# */
+	PAD_NC(GPP_H19, UP_20K),
+	PAD_NC(GPP_H20, UP_20K),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, UP_20K),
+	PAD_NC(GPP_H23, UP_20K),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c b/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c
new file mode 100644
index 0000000000..1b9386d388
--- /dev/null
+++ b/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek ALC293 */
+	0x10ec0293, /* Vendor ID */
+	0x15581401, /* Subsystem ID */
+	13, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15581401),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x01a1913c),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41748245),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+	/* Intel GPU HDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
new file mode 100644
index 0000000000..e85cf63623
--- /dev/null
+++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
@@ -0,0 +1,75 @@
+chip soc/intel/cannonlake
+	device domain 0 on
+		subsystemid 0x1558 0x1401 inherit
+
+		device pci 14.0 on      # USB xHCI
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1
+			register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3
+			register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3
+		end
+		device pci 15.0 on # I2C #0
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN040D""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+		end
+		device pci 17.0 on      # SATA
+			register "SataSalpSupport" = "1"
+			# Port 2 (J_SSD2)
+			register "SataPortsEnable[1]" = "1"
+			register "SataPortsDevSlp[1]" = "1"
+			# Port 3 (J_SSD1)
+			register "SataPortsEnable[2]" = "1"
+			register "SataPortsDevSlp[2]" = "1"
+		end
+		device pci 1c.5 on      # PCI Express Port 6
+			device pci 00.0 on end # x1 Card reader
+			register "PcieRpEnable[5]" = "1"
+			register "PcieRpLtrEnable[5]" = "1"
+			register "PcieClkSrcUsage[3]" = "5"
+			register "PcieClkSrcClkReq[3]" = "3"
+			register "PcieRpSlotImplemented[5]" = "1"
+		end
+		device pci 1c.7 on      # PCI Express Port 8
+			device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
+			register "PcieRpEnable[7]" = "1"
+			register "PcieRpLtrEnable[7]" = "1"
+			register "PcieClkSrcUsage[2]" = "7"
+			register "PcieClkSrcClkReq[2]" = "2"
+			register "PcieRpSlotImplemented[7]" = "1"
+			chip drivers/wifi/generic
+				device pci 00.0 on end
+			end
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
+		end
+		device pci 1d.0 on      # PCI Express Port 9
+			device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[4]" = "8"
+			register "PcieClkSrcClkReq[4]" = "4"
+			register "PcieRpSlotImplemented[8]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
+		end
+		device pci 1d.4 on      # PCI Express Port 13
+			device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
+			register "PcieRpEnable[12]" = "1"
+			register "PcieRpLtrEnable[12]" = "1"
+			register "PcieClkSrcUsage[5]" = "12"
+			register "PcieClkSrcClkReq[5]" = "5"
+			register "PcieRpSlotImplemented[12]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
+		end
+	end
+end
diff --git a/src/mainboard/system76/cml-u/variants/lemp9/romstage.c b/src/mainboard/system76/cml-u/variants/lemp9/romstage.c
new file mode 100644
index 0000000000..2be3353d40
--- /dev/null
+++ b/src/mainboard/system76/cml-u/variants/lemp9/romstage.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	.spd[0] = {
+		.read_type = READ_SPD_CBFS,
+		.spd_spec = { .spd_index = 0 },
+	},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = { .spd_smbus_address = 0xa4 },
+	},
+	.rcomp_resistor = { 121, 81, 100 },
+	.rcomp_targets = { 100, 40, 20, 20, 26 },
+	.dq_pins_interleaved = 1,
+	.vref_ca_config = 2,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}