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authorFelix Singer <felixsinger@posteo.net>2024-06-23 04:59:03 +0200
committerFelix Singer <felixsinger@posteo.net>2024-06-26 11:44:08 +0000
commitdf7de392ef5f8e1654df96a1a050820eb3779012 (patch)
tree341c3b10cc90f3831a9aadbb90d50d4edb0b47f4 /src/mainboard/supermicro/x11-lga1151-series
parentdcddc53fde2d559beef998d3c17e9b7a227e3665 (diff)
skl mainboards/dt: Move SATA related settings into SATA device scope
Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro/x11-lga1151-series')
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/devicetree.cb26
1 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
index 1a8be1dbb4..29759fd9fc 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -3,18 +3,6 @@ chip soc/intel/skylake
# FSP Configuration
register "SkipExtGfxScan" = "1"
- # SATA configuration
- register "SataSalpSupport" = "1"
- register "SataPortsEnable" = "{
- [0] = 1,
- [1] = 1,
- [2] = 1,
- [3] = 1,
- [4] = 1,
- [5] = 1,
- [6] = 1,
- [7] = 1,
- }"
# LPC
register "serirq_mode" = "SERIRQ_CONTINUOUS"
@@ -31,7 +19,19 @@ chip soc/intel/skylake
device ref south_xhci on end
device ref thermal on end
device ref heci1 on end
- device ref sata on end
+ device ref sata on
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable" = "{
+ [0] = 1,
+ [1] = 1,
+ [2] = 1,
+ [3] = 1,
+ [4] = 1,
+ [5] = 1,
+ [6] = 1,
+ [7] = 1,
+ }"
+ end
device ref lpc_espi on
chip superio/common
device pnp 2e.0 on end