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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-02 22:17:01 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-04 01:36:04 +0000 |
| commit | 65fd33f95fa85cd867cb434fe03b0c5f691b3fbc (patch) | |
| tree | 70c06f295f47ecd339af9fbfbd3aef257c3aec6f /src/mainboard/siemens | |
| parent | c0dbd4cb562b6c2d569eeb12562bfa3eb27925c9 (diff) | |
vendorcode/amd/fsp/cezanne: add UPD structs from FSP build
There will be incompatible changes during the further development of the
coreboot+FSP support for Cezanne, but we do need the FSP-M UPD struct
size to match the one in the FSP header. See CB:50241 for details.
Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50242
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens')
0 files changed, 0 insertions, 0 deletions