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authorMario Scheithauer <mario.scheithauer@siemens.com>2018-11-09 10:25:15 +0100
committerWerner Zeh <werner.zeh@siemens.com>2018-11-12 07:27:10 +0000
commit3a499725f0fded9cba9b76816f469138149e00f8 (patch)
treef04093f2afe3e419b991050254923169058a67b8 /src/mainboard/siemens
parentfe7367801c3f6f0f876c6258aa924c085e19ed89 (diff)
siemens/mc_apl4: Enable all PCIe root ports
Enable all PCIe root ports for this mainboard. Change-Id: I7f6feb2f0d4c45f32d9454838e67e1a244b2712b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens')
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
index 8c219af484..61e8c7107e 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
@@ -60,12 +60,12 @@ chip soc/intel/apollolake
device pci 0e.0 off end # - Audio
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
- device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY
- device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY
- device pci 13.2 off end # - RP 4 - PCIe-A 2
- device pci 13.3 off end # - RP 5 - PCIe-A 3
- device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge
- device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA
+ device pci 13.0 on end # - RP 2 - PCIe A 0
+ device pci 13.1 on end # - RP 3 - PCIe A 1
+ device pci 13.2 on end # - RP 4 - PCIe-A 2
+ device pci 13.3 on end # - RP 5 - PCIe-A 3
+ device pci 14.0 on end # - RP 0 - PCIe-B 0
+ device pci 14.1 on end # - RP 1 - PCIe-B 1
device pci 15.0 on end # - XHCI
device pci 15.1 off end # - XDCI
device pci 16.0 on # - I2C 0