diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2017-10-23 16:10:04 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2017-11-03 07:11:47 +0000 |
| commit | d958300590023fe5aedbe1cfae6ea0f62b2e207f (patch) | |
| tree | 12ba393ca95c614ac056fe2cfb266272110e0ba5 /src/mainboard/siemens | |
| parent | d0e51330edba4981dce6f5e539049afe08d2e2de (diff) | |
siemens/mc_apl1: Add legacy IRQ routing for PCI devices
On this mainboard there are PCI devices, which are connected to the PCIe
root port via a PCIe-2-PCI bridge. One of the devices only supports
legacy interrupt routing. For this reason we have to adjust the PIR6
register (0x314c) which is responsible for PCIe device 13h and 14h. This
means that the interrupt routing will also be the same for both PCIe
devices. The bridge is connected to PCIe root port 4 (Device 14.0).
The following routing is required:
INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#->PIRQA#
Change-Id: I5464c9a2669773bc1e6cd4b4d29d1be838dbfa27
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/mainboard.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index f77ef75d3e..60a62a7874 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -21,7 +21,9 @@ #include <hwilib.h> #include <i210.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> #include <soc/pci_devs.h> +#include <soc/pcr_ids.h> #include <string.h> #include <bootstate.h> #include <timer.h> @@ -142,6 +144,12 @@ static void mainboard_final(void *chip_info) cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); } + + /* + * PIR6 register mapping for PCIe root ports + * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# + */ + pcr_write16(PID_ITSS, 0x314c, 0x0321); } static void wait_for_legacy_dev(void *unused) |