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| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-07-11 16:03:52 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:36:34 +0200 |
| commit | 0cf11cb7837d34589da466dcdcfa0aecc1e6c3db (patch) | |
| tree | 2f59435e55ce2d914f09a093358998a1d9a89a4c /src/mainboard/siemens/sitemp_g1p1/fadt.c | |
| parent | 81d1e09113bc12ea9427e9522d4f5eab982c145e (diff) | |
soc/intel/apollolake: add offset of GPIO_TIER1_SCI_EN bit
This patch adds the support for gpio_tier1_sci_en bit which
needs to be set before going to sleep so that when
gpio_tier1_sci_sts bit gets set platform can wake
from S3.
BUG = chrome-os-partner:53992
TEST = Platform wakes from S3 on lidopen,key press.
Tested on Amenia and Reef boards.
Change-Id: I3ba79fa53ca8817149d585fa795a8f427c128dcb
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15612
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/siemens/sitemp_g1p1/fadt.c')
0 files changed, 0 insertions, 0 deletions