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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-01 13:57:45 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-02 14:50:01 +0000 |
| commit | 639cc9c6baea73a467cacd4d3b21419da059f8ab (patch) | |
| tree | 09ea54616978256e8480e2962b8036409bf5478b /src/mainboard/siemens/mc_apl1 | |
| parent | 00b5f533615eac269d73af5f0e6c69cb498ca7d9 (diff) | |
soc/intel/baytrail,braswell: Sync PCI memory region in ASL
Baytrail had (only) occurence of DwordMemory vs DWordMemory.
Braswell one had bogus comments about the PCI memory range.
The actual region details are dynamically filled in _CRS.
Change-Id: I8d1bf45c6e5520c0b7643602843c665bfb81f9da
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1')
0 files changed, 0 insertions, 0 deletions