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| author | Shaunak Saha <shaunak.saha@intel.com> | 2020-03-25 11:42:12 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-30 08:37:39 +0000 |
| commit | d72cca0c44bc944fdfbdcbc4b264ba0c3727649b (patch) | |
| tree | f7ed68bc36461ddde13b35e949943b6200a126c7 /src/mainboard/siemens/mc_apl1/board_info.txt | |
| parent | 1e40a115778865e60a13cb71fdf18eb3ddf1751f (diff) | |
mb/tglrvp: Add GPE configuration
Update the GPE configuration for dw0, dw1 and dw2.
BUG=None
TEST=build and boot tglrvp
Change-Id: I8b406bcbd710e84cec91a8c2d1557902e929f7cc
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39844
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1/board_info.txt')
0 files changed, 0 insertions, 0 deletions